Fairchild Semiconductor since Feb 2009
Yield Integration Project Manager
UPS Group 2008 - 2009
Unemployed
National Semiconductor Apr 2006 - Nov 2008
DICE Group Section Manager
National Semiconductor Feb 1996 - Nov 2008
Process Section Manager
National Semiconductor Jun 2000 - Apr 2006
Defect Integration Section Manager
Education:
Johnson and Wales University 1990 - 1994
Bachelor, Electrical Engineering
Central New England College 1984 - 1990
Associates, Electrical Engineering
Skills:
Semiconductors Spc Manufacturing Six Sigma Design of Experiments Process Engineering Semiconductor Industry Lean Manufacturing Fmea Failure Analysis Testing Yield Engineering Product Development Engineering Management Management Process Control R&D Leadership Troubleshooting Product Management Integration Quality Control Strategic Planning Digital Electronics
Mar 2009 to 2000 Diffusion, EPI, ET and DDP Group Manager ResponsibilitiesNational Semiconductor South Portland, ME Nov 1996 to Feb 2009 Manufacturing Process Engineering Group - Section ManagerNational Semiconductor
2002 to 2006 Section ManagerNational Semiconductor
1996 to 2002 Defect Reduction Group - Staff Level Yield EngineerDigital Semiconductor Hudson, MA 1984 to 1996 DRAT Group - Sr. Defect EngineerDigital Semiconductor
1988 to 1994 Process EngineerDigital Semiconductor
1984 to 1988 Operator
Education:
Johnson & Wales University North Smithfield, RI 1989 to 1992 Bachelors in Electrical EngineeringCentral New England College Worcester, MA 1984 to 1989 Associates in Electrical Engineering