Rene Gerard Meessen

US Patent:

20210073171, Mar 11, 2021

Filed:

Sep 9, 2020

Appl. No.:

17/015973

Inventors:

- Campbell CA, US
Steven K. Knapp - Soquel CA, US
Raymond J. Andraka - North Kings Town RI, US
Alexei Beliaev - Campbell CA, US
Martin A. Franz - Sunnyvale CA, US
Rene Meessen - San Francisco CA, US
Frederick Curtis Furtek - Menlo Park CA, US

International Classification:

G06F 15/80
G06F 7/523
G06F 7/50
G06F 9/38
G06F 9/30
G06F 9/48
G06F 9/54
G06F 5/01
H03K 19/21

Abstract:

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.