Rene N Vega

US Patent:

7313793, Dec 25, 2007

Filed:

Jul 11, 2002

Appl. No.:

10/193531

Inventors:

Eric P. Traut - San Carlos CA, US
Rene A. Vega - Scotts Valley CA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/455

US Classification:

718 1, 709201, 711 6, 711165

Abstract:

A method is provided for increasing the efficiency of virtual machine processing. A parent virtual machine is provided on a host computer. The parent virtual machine is temporarily or permanently suspended. A child virtual machine is created at a new location by forking the parent virtual machine. The child virtual machine may not initially include all the stored data that is associated with the parent virtual machine.

US Patent:

7373446, May 13, 2008

Filed:

Nov 5, 2004

Appl. No.:

10/982081

Inventors:

Bradley S. Post - San Francisco CA, US
Rene A. Vega - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 13/24
G06F 9/455

US Classification:

710261, 710266, 718 1

Abstract:

In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.

US Patent:

7761638, Jul 20, 2010

Filed:

Apr 22, 2008

Appl. No.:

12/107660

Inventors:

Bradley S. Post - San Francisco CA, US
Rene A. Vega - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 13/24
G06F 13/32
G06F 9/455

US Classification:

710261, 710266, 718 1

Abstract:

In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.