Renee C Garcia

US Patent:

20140332956, Nov 13, 2014

Filed:

May 13, 2013

Appl. No.:

13/893193

Inventors:

Tieyu ZHENG - Redmond WA, US
Sumit KUMAR - Phoenix AZ, US
Sridhar NARA - San Jose CA, US
Renee D. GARCIA - Gilbert AZ, US
Manohar S. KONCHADY - Chandler AZ, US
Suresh B. YERUVA - Chandler AZ, US
Lynn H. CHEN - Gilbert AZ, US
Tyler N. OSBORN - Gilbert AZ, US
Sairam AGRAHARAM - Chandler AZ, US

International Classification:

H01L 23/498
H01L 21/768

US Classification:

257738, 438613

Abstract:

An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).