Ricardo E Ramirez

US Patent:

6412067, Jun 25, 2002

Filed:

Aug 11, 1998

Appl. No.:

09/132042

Inventors:

Ricardo Ramirez - Cupertino CA
Michael J. Morrison - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1500

US Classification:

712245

Abstract:

An executed first instruction having a first logical operand as a destination is retired. A register assigned to the first logical operand is identified to back out of an architectural state. The identifying may be performed when an executed second instruction having a second logical operand as a destination is ready to retire or is retired. The register may be assigned to a third logical operand for an instruction to be executed.

US Patent:

6691223, Feb 10, 2004

Filed:

Jul 30, 1999

Appl. No.:

09/365260

Inventors:

Elango Ganesan - Sunnyvale CA
Ricardo Ramirez - Sunnyvale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 948

US Classification:

712244, 712233

Abstract:

The present invention is a method and apparatus for processing full exceptions in a partial parallel processor operating on parallel operands which form into N groups. The method comprising: (a) generating P partial exception states for P partial exceptions from the partial parallel processor operating on the N groups of the parallel operands; the P partial exceptions correspond to the full exceptions; and (b) handling the P partial exceptions based on the P partial exception states.

US Patent:

6754774, Jun 22, 2004

Filed:

Mar 25, 2002

Appl. No.:

10/105497

Inventors:

Fred Gruner - Palo Alto CA
Ricardo Ramirez - Sunnyvale CA

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711119, 711121, 711129, 711162

Abstract:

A system includes a memory, a sequencer, and a set of application engines in communication with the sequencer and memory. The set of application engines includes a streaming output engine with a storage engine, alignment circuit, and data buffer. The storage engine includes a memory opcode output and memory address output in communication with the memory. The storage engine employs these outputs to access the memory by supplying memory transaction opcodes and memory addresses. The alignment circuit receives data from other application engines in the set of application engines. In operation, the alignment circuit aligns data transfers from an application engine into a data word. The data buffer stores data words from the alignment circuit and transfers them to locations accessed in the memory by the storage engine.

US Patent:

6839808, Jan 4, 2005

Filed:

Jul 6, 2001

Appl. No.:

09/900481

Inventors:

Fred Gruner - Palo Alto CA, US
David Hass - Santa Clara CA, US
Robert Hathaway - Santa Clara CA, US
Ricardo Ramirez - Sunnyvale CA, US
Nazar Zaidi - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711130, 711122, 711138

Abstract:

A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

US Patent:

6901482, May 31, 2005

Filed:

Mar 25, 2002

Appl. No.:

10/106925

Inventors:

Fred Gruner - Palo Alto CA, US
David Hass - Santa Clara CA, US
Robert Hathaway - Santa Clara CA, US
Ramesh Panwar - Pleasanton CA, US
Ricardo Ramirez - Sunnyvale CA, US
Nazar Zaidi - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F013/00

US Classification:

711130, 711119, 711154

Abstract:

A system includes a plurality of processing clusters and a snoop controller. A first processing cluster in the plurality of processing clusters includes a first tier cache memory coupled to a second tier cache memory. The system employs a store-create operation to obtain sole ownership of a full cache line memory location for the first processing cluster, without retrieving the memory location from other processing clusters. The system issues the store-create operation for the memory location to the first tier cache. The first tier cache forwards a memory request including the store-create operation command to the second tier cache. The second tier cache determines whether the second tier cache has sole ownership of the memory location. If the second tier cache does not have sole ownership of the memory location, ownership of the memory location is relinquished by the other processing clusters with any ownership of the memory location.

US Patent:

6901488, May 31, 2005

Filed:

Mar 25, 2002

Appl. No.:

10/105587

Inventors:

Fred Gruner - Palo Alto CA, US
Robert Hathaway - Santa Clara CA, US
Ricardo Ramirez - Sunnyvale CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F013/00

US Classification:

711154, 711119, 711130

Abstract:

A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a sequencer coupled to a set of application engines for performing operations assigned to the compute engine. The sequencer is coupled to application engines through a set of data, enable, and control interfaces. An arbiter couples the sequencer and application engines to memory. Alternatively, the coprocessor may include multiple sequencers, with each sequencer being coupled to a different set of application engines. One set of application engines includes a media access controller for communicating with a network and a data transfer engine coupling the media access controller to the arbiter. In one implementation, application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

US Patent:

6901489, May 31, 2005

Filed:

Mar 25, 2002

Appl. No.:

10/105862

Inventors:

Fred Gruner - Palo Alto CA, US
Ricardo Ramirez - Sunnyvale CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F013/00

US Classification:

711154, 711119, 711130

Abstract:

A system includes a memory, a sequencer, and a set of application engines in communication with the sequencer and memory. The set of application engines includes a streaming input engine for retrieving data from the memory and supplying the data to the set of application engines. In one embodiment, the streaming input engine includes a fetch engine with a memory opcode output and address output for accessing cache memory. The streaming input engine also includes an alignment circuit for buffering and aligning data retrieved from the memory. The alignment circuit includes a data buffer, register, byte selector, and shifter. The data buffer stores data accessed by the fetch engine. The register stores old data from the data buffer's output when the buffer sources new data. The byte selector selects data from the data buffer and the register. The shifter receives data selected by the byte selector and shifts a number of the bytes onto an output for retrieval by an output register coupled to the set of application engines.

US Patent:

6920529, Jul 19, 2005

Filed:

Mar 25, 2002

Appl. No.:

10/105857

Inventors:

Fred Gruner - Palo Alto CA, US
Robert Hathaway - Santa Clara CA, US
Ricardo Ramirez - Sunnyvale CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F013/00

US Classification:

711122, 711147, 711202, 711203

Abstract:

A coprocessor transfers data between media access controllers and a set of cache memory without accessing main memory. The coprocessor includes a reception media access controller that receives data from a network and a transmission media access controller that transmits data to a network. A streaming output data transfer engine in the coprocessor transfers data from the reception media access controller to cache memory. A streaming input data transfer engine in the coprocessor transfers data from cache memory to the transmission media access controller. The coprocessor's data transfer engines transfer data between cache memory and the media access controllers in a single data transfer operation—eliminating the need to store data in an intermediary memory location between the cache memory and data transfer engines. In one implementation, the coprocessor is employed in a compute engine that performs different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.