Richard Eric Beck

US Patent:

6431908, Aug 13, 2002

Filed:

Sep 15, 2000

Appl. No.:

09/663818

Inventors:

Mark J. Beck - Los Gatos CA
Richard V. Beck - Saratoga CA

Assignee:

Product Systems Incorporated - Campbell CA

International Classification:

H01R 300

US Classification:

439500, 439 66, 310355

Abstract:

A system for making electrical connections to a piezoelectric crystal in a megasonic transducer. The system comprises a printed circuit board, one or more first spring connectors and one or more second spring connectors. The printed circuit board has a first copper trace plated on it that is adapted for electrical connection to the active terminal of an RF generator. A second copper trace is plated on the printed circuit board and is adapted for electrical connection to the ground terminal of the RF generator. The first spring connectors are electrically connected to the first trace and are positioned to make electrical contact with the back side of the piezoelectric crystal. The second spring connectors are electrically connected to the second trace and are positioned to make electrical contact with the front side of the piezoelectric crystal, so that the piezoelectric crystal is exited when the RF generator is in operation.

US Patent:

46672206, May 19, 1987

Filed:

Apr 27, 1984

Appl. No.:

6/605018

Inventors:

James C. K. Lee - Los Altos CA
Gene M. Amdahl - Atherton CA
Carlton G. Amdahl - Saratoga CA
Richard L. Beck - Cupertino CA

Assignee:

Trilogy Computer Development Partners, Ltd. - Cupertino CA

International Classification:

H01L 2348
H01L 2352
H01L 2340
H01L 2312

US Classification:

357 68

Abstract:

A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.

US Patent:

47545461, Jul 5, 1988

Filed:

Mar 18, 1986

Appl. No.:

6/841081

Inventors:

James C. K. Lee - Los Altos Hills CA
Richard Beck - Cupertino CA
Chune Lee - San Francisco CA
Edward Hu - Sunnyvale CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01R 1348

US Classification:

29877

Abstract:

An anisotropic elastomeric conductor is fabricated by stacking a plurality of metal sheets and elastomeric sheets, where the metal sheets have a plurality of parallel electrically conductive elements formed therein. By coating a curable elastomeric resin on the metal sheets, and then curing the resulting layered structure, a solid elastomeric block having a plurality of parallel electrically conductive elements running its length is obtained. Individual elastomeric conductors suitable for interfacing between electronic components are obtained by slicing the block in a direction perpendicular to the conductors. The conductor slices so obtained are particularly suitable for interfacing between electronic devices having planar arrays of electrical contact pads.

US Patent:

47789506, Oct 18, 1988

Filed:

Apr 17, 1986

Appl. No.:

6/853313

Inventors:

James C. K. Lee - Los Altos Hills CA
Richard Beck - Cupertino CA
Chune Lee - San Francisco CA
Edward Hu - Sunnyvale CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01B 700

US Classification:

174356C

Abstract:

Electronic assemblies are fabricated by stacking alternate connecting layers and component layers. The component layers may be virtually any rigid structure having contact regions formed on at least one face thereof. The connecting layers are formed from anisotropic elastomeric conductors which in turn are fabricated by stacking a plurality of conductive sheets and insulating sheets, where the conductive sheets have a plurality of parallel electrically conductive elements formed therein. By introducing a curable elastomeric resin into the stacked structure so formed, and then curing the elastomer, a solid elastomeric block having a plurality of parallel electrically conductive elements running its length is obtained. Individual elastomeric conductors suitable as connecting layers interfacing between adjacent component layers are obtained by slicing the block in a direction perpendicular to the conductors.

US Patent:

46928391, Sep 8, 1987

Filed:

Jun 24, 1985

Appl. No.:

6/748087

Inventors:

James C. K. Lee - Los Altos CA
Richard L. Beck - Cupertino CA
Francisca Tung - Los Gatos CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H05K 720
H01L 2312

US Classification:

361386

Abstract:

A multiple chip interconnection system and package for interconnecting and cooling integrated circuits includes an electrically-conductive plate 10 having an upper surface 12. On the upper surface 12, a first layer of polyimide 16 or other electrically-insulating material is deposited. One or more layers of electrical interconnections 17, 18, 21, 22, and insulating material 19, 24, are then disposed on the insulating material 16 to provide a network of electrical connections embedded in insulating material, yet which is sufficiently thin to offer minimal thermal resistance to the transfer of heat from integrated circuits mounted thereon to the plate 10. After the layers of interconnections are completed, one or more conductive planes are deposited across the interconnections to serve as a mounting surface for the integrated circuits and to distribute power and ground signals as necessary. One or more integrated circuits 40 are then attached to the plane 32 and suitable interconnections made between the integrated circuits and desired regions 34 of the plane. The package is completed by attaching an air- or water-cooled heat sink 54 to the opposite side of plate 10 from the integrated circuits.

US Patent:

49548735, Sep 4, 1990

Filed:

Jan 25, 1988

Appl. No.:

7/147779

Inventors:

James Lee - Los Altos Hills CA
Richard Beck - Cupertino CA
Chune Lee - San Francisco CA
Edward Hu - Sunnyvale CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01L 2312
H01L 2314

US Classification:

357 72

Abstract:

An anisotropic elastomeric conductor is fabricated by stacking a plurality of first and second sheets, where the first sheets include a plurality of parallel electrically conductive fibers and the second sheets are composed of electrically insulating material. By introducing a curable elastomeric resin into the layered structure of sheets, and then curing the resin, a solid elastomeric block having a plurality of parallel electrically conductive fibers running its length is obtained. Individual elastomeric conductors suitable for interfacing between electronic components are obtained by slicing the block in a direction perpendicular to the conductors. The conductor slices so obtained are particularly suitable for interfacing between electronic devices having planar arrays of electrical contact pads.

US Patent:

50141619, May 7, 1991

Filed:

Feb 7, 1990

Appl. No.:

7/477133

Inventors:

James C. K. Lee - Los Altos Hills CA
Gene M. Amdahl - Atherton CA
Richard Beck - Cupertino CA
Chune Lee - San Francisco CA
Edward Hu - Sunnyvale CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H05K 720

US Classification:

361388

Abstract:

A semiconductor mounting system is provided for the detachable surface mounting of one or more semiconductor dies on a conductor substrate, such as a ceramic substrate or printed circuit board. The system employs a resilient, anisotropic conductor pad which is interposed between the semiconductor die and the conductor substrate. The conductor pad is capable of conducting electric signals in one direction only, and insulates in the other two orthogonal directions. Thus, by compressing the semiconductor die and resilient conductor pad against the conductor substrate, electrical contact is established between contacts on the semiconductor die and corresponding contacts on the conductor substrate. In the preferred embodiment, additional conductor pads are placed over the semiconductor dies, and a heat sink placed over the second conductor pads. In this way, the semiconductor dies are mounted in a resilient structure for protection, while heat dissipation is enhanced by the metallic elements in the second conductor pad.

US Patent:

47291664, Mar 8, 1988

Filed:

Jul 22, 1985

Appl. No.:

6/757600

Inventors:

James Lee - Los Altos Hills CA
Richard Beck - Cupertino CA
Chune Lee - San Francisco CA
Edward Hu - Sunnyvale CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01R 1348

US Classification:

29877

Abstract:

An anisotropic elastomeric conductor is fabricated by stacking a plurality of first and second sheets, where the first sheets include a plurality of parallel electrically conductive fibers and the second sheets are composed of electrically insulating material. By introducing a curable elastomeric resin into the layered structure of sheets, and then curing the resin, a solid elastomeric block having a plurality of parallel electrically conductive fibers running its length is obtained. Individual elastomeric conductors suitable for interfacing between electronic components are obtained by slicing the block in a direction perpendicular to the conductors. The conductor slices so obtained are particularly suitable for interfacing between electronic devices having planar arrays of electrical contact pads.