Richard L Daniel

US Patent:

49640178, Oct 16, 1990

Filed:

Apr 26, 1989

Appl. No.:

7/344234

Inventors:

James A. Jindrick - Tucson AZ
L. Dennis Page - Tucson AZ
Richard A. Daniel - Tucson AZ

Assignee:

Intelligent Instrumentation, Inc. - Tucson AZ

International Classification:

H05K 500

US Classification:

361390

Abstract:

An adaptable housing for a PC clone computer or the like includes easily removable front and rear panel sections and a cover, all of which are adapted to be conveniently drilled, punched, etc. for internal or external attachment of switches, connectors, and/or other user-installed equipment. A removable card cage resting on a removable base receives a variety of PC boards or other equipment in suitable slots and allows internal routing of cables, conductors, and the like from printed circuit boards mounted in the card cage to slots and/or other printed circuit boards on or connected to a horizontal mother board or back plane attached to the bottom panel of the housing. One or two boxes are attached to the front panel or the bottom panel by means of suitable brackets to carry disk drive units or other equipment. Resilient grommets mounted in suitable openings of the boxes receive heads of screws attached to side or bottom surfaces of the disk drives or other equipment to provide economical, vibration-absorbing shock mounts.

US Patent:

48477508, Jul 11, 1989

Filed:

Feb 13, 1986

Appl. No.:

6/829408

Inventors:

Richard A. Daniel - Tucson AZ

Assignee:

Intelligent Instrumentation, Inc. - Tucson AZ

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A peripheral DMA (direct memory access) system having a computer with an internal DMA controller and only one channel available for external DMA operations includes: a peripheral DMA controller coupled between the computer address bus and a peripheral address bus, and also between the computer data bus and a peripheral data bus. The peripheral DMA controller includes a dual port "frame map memory" in which addresses of various peripheral devices are sequentially stored prior to initiating a DMA operation wherein data is rapidly transferred from various peripheral devices having nonsequential addresses to sequential locations of the computer memory or vice versa.