Richard H Egloff

US Patent:

6559068, May 6, 2003

Filed:

Jun 28, 2001

Appl. No.:

09/894089

Inventors:

Dev Alok - Danbury CT
Emil Arnold - Chappaqua NY
Richard Egloff - Yorktown Heights NY
Satyendranath Mukherjee - Yorktown Heights NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 21469

US Classification:

438770, 438769, 438771

Abstract:

A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

US Patent:

54551935, Oct 3, 1995

Filed:

Nov 17, 1994

Appl. No.:

8/344206

Inventors:

Richard H. Egloff - Yonkers NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H01L 2176

US Classification:

437 63

Abstract:

A silicon-on-insulator (SOI) material is formed from a bonded silicon wafer structure which includes, in order, a silicon handler substrate, an insulating oxide layer, a silicon device layer, a highly-doped silicon etch stop layer, and a top silicon substrate. The bonded silicon wafer structure is etched in a first anisotropic etching step to remove the top silicon substrate and expose the etch stop layer. Subsequently, a second anisotropic etching step is performed to remove a major portion but less than all of the etch stop layer, with the second anisotropic etching step continuing only until a substantially maximum degree of thickness uniformity is obtained in a remaining portion of the etch stop layer. The remaining portion of the etch stop layer is then removed, to yield a silicon-on-insulator material having a high degree of thickness uniformity.

US Patent:

59096276, Jun 1, 1999

Filed:

May 18, 1998

Appl. No.:

9/080783

Inventors:

Richard Egloff - Yorktown Heights NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H01L 2176
H01L 21265
H01L 21425

US Classification:

438406

Abstract:

Thin layers of semiconductor material having a high degree of surface uniformity are produced by: implantion of deuterium ions into a body of semiconductor material to form a buried region of high stress, the buried region defining a thin outer region of the body; attaching a stiffening carrier to the thin outer region of the semiconductor body; and heating the body at 350-450 degrees C. to separate the thin outer region. The separated layer is useful in the production of silicon-on-insulator semiconductor devices, and silicon-on-glass devices for liquid crystal display and microwave applications.

US Patent:

63134896, Nov 6, 2001

Filed:

Nov 16, 1999

Appl. No.:

9/440767

Inventors:

Theodore Letavic - Putnam Valley NY
Mark Simpson - Ossining NY
Richard Egloff - Yorktown Heights NY
Andrew Mark Warwick - Stockport, GB

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H01L 3300
H01L 2978

US Classification:

257287

Abstract:

A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by a surface insulation region. In order to increase breakdown voltage and/or reduce "on" resistance, the lateral drift region is provided with at least a portion with a retrograde doping profile. This may advantageously be done by doping the semiconductor substrate, oxidizing the substrate to form the buried insulating layer, forming the SOI layer on the buried insulating layer, and thermally diffusing dopant from the buried insulating layer into the SOI layer.