Richard J Farrell

US Patent:

20220236639, Jul 28, 2022

Filed:

Jan 22, 2021

Appl. No.:

17/155931

Inventors:

- Tokyo, JP
Richard Farrell - Albany NY, US

International Classification:

G03F 7/00
C09D 153/00
C08L 53/00
C08L 25/06
B81C 1/00

Abstract:

A method for forming a device includes blending, in a mixer within a fabrication facility, a first liquid including a first block copolymer with a second liquid including a second block copolymer to form a first mixture. The first block copolymer includes a first homopolymer and a second homopolymer, where the first homopolymer has a first mole fraction in the first liquid. The second block copolymer includes the first homopolymer and the second homopolymer, the first homopolymer having a second mole fraction in the second liquid, the first mole fraction being different from the second mole fraction. The method includes placing a substrate over a substrate holder of a processing chamber within the fabrication facility; and coating the substrate with the first mixture within the processing chamber.

US Patent:

20210407804, Dec 30, 2021

Filed:

Jun 30, 2020

Appl. No.:

16/916452

Inventors:

- Tokyo, JP
Richard Farrell - Albany NY, US

International Classification:

H01L 21/033
G03F 7/09
G03F 7/11
G03F 7/20
G03F 7/26
H01L 21/027

Abstract:

A method of forming a device includes forming a hard mask layer over an underlying layer of a substrate, forming an anti-reflective coating layer over the hard mask layer, forming a patterned resist layer over the anti-reflective coating layer, and forming a mandrel including the anti-reflective coating layer by patterning the anti-reflective coating layer using the patterned resist layer as an etch mask. The method includes forming a sidewall spacer on the mandrel including the anti-reflective coating layer, forming a freestanding spacer on the hard mask layer by removing the mandrel from the anti-reflective coating layer, and using the freestanding spacer as an etch mask, patterning the underlying layer of the substrate.

US Patent:

20210088904, Mar 25, 2021

Filed:

Sep 17, 2020

Appl. No.:

17/023470

Inventors:

- Tokyo, JP
Jodi GRZESKOWIAK - Schenectady NY, US
Daniel FULFORD - Ballston Lake NY, US
Richard A. FARRELL - Nassau NY, US
Jeffrey SMITH - Clifton Park NY, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G03F 7/039
H01L 21/027
G03F 7/16
G03F 7/30
G03F 7/20

Abstract:

A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.

US Patent:

20210057226, Feb 25, 2021

Filed:

Jul 24, 2020

Appl. No.:

16/938049

Inventors:

- Tokyo, JP
Eric Chih-Fang Liu - Albany NY, US
Richard Farrell - Albany NY, US
Soo Doo Chae - Albany NY, US

International Classification:

H01L 21/3065
H01L 21/02
H01L 21/033

Abstract:

A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

US Patent:

20190295846, Sep 26, 2019

Filed:

Mar 18, 2019

Appl. No.:

16/356477

Inventors:

- Tokyo, JP
Richard Farrell - Albany NY, US
Kandabara Tapily - Albany NY, US
Angelique Raley - Albany NY, US
Sophie Thibaut - Albany NY, US

International Classification:

H01L 21/033
H01L 21/308
H01L 21/66
H01L 21/67
H01L 21/677

Abstract:

A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment. Broadly, using selective/conformal deposition, etching, or implanting techniques to form a sidewall spacer pattern on a common manufacturing platform.

US Patent:

20190295906, Sep 26, 2019

Filed:

Mar 18, 2019

Appl. No.:

16/356465

Inventors:

- Tokyo, JP
Richard Farrell - Albany NY, US
Kandabara Tapily - Albany NY, US
Angelique Raley - Albany NY, US
Sophie Thibaut - Albany NY, US

International Classification:

H01L 21/66
H01L 21/033
H01L 21/67

Abstract:

A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment. Broadly, forming a sidewall spacer pattern based on the mandrel pattern.

US Patent:

20180323061, Nov 8, 2018

Filed:

May 3, 2018

Appl. No.:

15/970168

Inventors:

- Tokyo, JP
Sophie Thibaut - Albany NY, US
Richard Farrell - Albany NY, US

International Classification:

H01L 21/027
H01L 21/311
H01L 21/02
H01L 21/033

Abstract:

A method to implement self-aligned triple patterning techniques for the processing of substrates is provided. In one embodiment, a self-aligned triple processing technique utilizing an organic spacer is provided. The organic spacer may be formed utilizing any of a wide range of techniques including, but not limited to, plasma deposition and spin on deposition. In one embodiment, the organic spacer may be formed via a cyclic deposition etch process. In one embodiment, the self-aligned triple patterning technique may be utilized to form patterned structures on a substrate at pitches of 26 nm or less.

US Patent:

20180130708, May 10, 2018

Filed:

Nov 9, 2017

Appl. No.:

15/808473

Inventors:

- Tokyo, JP
Elliott Franke - Albany NY, US
Richard Farrell - Nassau NY, US

International Classification:

H01L 21/768
H01L 21/311
H01L 21/02
H01L 23/528
H01L 23/522

Abstract:

A formed back-end-of-line (BEOL) metal line layer may include a plurality of metal lines with dielectric oxide caps that are disposed in between each metal lines. To overlay an interconnecting layer of metal lines on a selected metal line of the BEOL metal line layer, a block copolymer (BCP) may be formed on a patterning layer. Thereafter, a selective etching of the formed BCP creates a recess above the selected metal line. The created recess facilitates the overlaying of the interconnecting layer of metal lines.