Richard A Fisher

US Patent:

6556046, Apr 29, 2003

Filed:

Sep 14, 2001

Appl. No.:

09/953059

Inventors:

Roger D. St. Amand - Tempe AZ
Steven R. Bible - Chandler AZ
Richard J. Fisher - Glendale AZ
Johannes A. Van Niekerk - Tempe AZ
Farron L. Dacus - Chandler AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H03K 190175

US Classification:

326 63, 327333

Abstract:

The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between a digital device and a radio frequency device (wireless RF digital device), and the circuitry of a system including the packaged devices. Even more particularly, the present invention relates to a wireless radio frequency digital device functional pathway configuration for the interface between the wireless radio frequency digital device and a system in which the wireless radio frequency digital device is embedded.

US Patent:

20030060185, Mar 27, 2003

Filed:

Sep 14, 2001

Appl. No.:

09/953058

Inventors:

Richard Fisher - Glendale AZ, US
Roger St. Amand - Tempe AZ, US
Steven Bible - Chandler AZ, US
Johannes Van Niekerk - Tempe AZ, US
Farron Dacus - Chandler AZ, US

International Classification:

H04B001/06

US Classification:

455/344000, 455/130000

Abstract:

A wireless control and/or data acquisition system in an integrated circuit comprises a digital device and a wireless device, e.g., a radio frequency (RF) device, an infrared device (IrDA), etc. A micro-electro-mechanical (MEM) device may also be included in the integrated circuit package. The MEM may be used as a sensor, non-volatile memory, a filter, a frequency determining resonator, and/or a control device in combination with the digital device. The digital device and RF device may have independent power and signal connections for signal isolation between the digital device and RF device. Standby and sleep modes for the digital device and RF device reduce power consumption and low voltage operation enables the use of a simple battery power source.

US Patent:

43342892, Jun 8, 1982

Filed:

Feb 25, 1980

Appl. No.:

6/124008

Inventors:

Ronald E. Lange - Phoenix AZ
Richard J. Fisher - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 700

US Classification:

364900

Abstract:

There is disclosed herein an apparatus for encoding, storing, updating and decoding data indicating the order of usage of memory locations as in a cache memory. An array of memory bits is encoded by a field programmable logic array each time a memory device or other peripheral is accessed by a method which need change only a portion of all the memory bits in a row. Each row corresponds to a group of memory locations or peripherals to be monitored. When the order of usage of a group of monitored locations is to be determined a field programmable logic array decodes the corresponding row and outputs a signal indicating the least recently used one of the memory locations of interest.

US Patent:

54887119, Jan 30, 1996

Filed:

Apr 1, 1993

Appl. No.:

8/041076

Inventors:

Kent D. Hewitt - Tempe AZ
Samuel E. Alexander - Gilbert AZ
Richard J. Fisher - Phoenix AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 1328
G06F 1336
G11C 1604

US Classification:

395430

Abstract:

A serial EEPROM (electrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller. Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller. Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.

US Patent:

53454138, Sep 6, 1994

Filed:

Apr 1, 1993

Appl. No.:

8/041069

Inventors:

Richard J. Fisher - Phoenix AZ
Samuel E. Alexander - Gilbert AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 1700

US Classification:

365 96

Abstract:

The usability of an electrically erasable programmable semiconductor memory device is assured after shipment from the factory despite implementing the device with a user option to selectively configure the security, endurance, organization, density or protocol of the memory array of the device. The user selected configuration is made permanent and inaccessible for change by programming associated normally reversible configuration fuses which are rendered incapable of being reprogrammed (reversed) thereafter by the automatic and simultaneous programming of a lockout fuse. Final testing of the device at the factory is permitted by an override of the lockout fuse during testing of the operation of the configuration fuses, and, when the testing is completed, returning, under program control, all fuses to a default condition in which the configuration fuses are limited to one-time programmability as a consequence of automatic simultaneous programming of the lockout fuse and configuration fuses at any time after shipment of the device from the factory.

US Patent:

53717090, Dec 6, 1994

Filed:

Apr 1, 1993

Appl. No.:

8/041067

Inventors:

Richard J. Fisher - Phoenix AZ
Samuel E. Alexander - Gilbert AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 514

US Classification:

365226

Abstract:

Power consumption of a serial EEPROM is reduced while simultaneously precluding data corruption during write operations. These results are achieved by operating a brownout detector in the device to sense EEPROM supply voltage below a predetermined level and thereupon to place the EEPROM in a reduced power mode, but only during an interval that a write sequence is taking place. Such an interval includes loading of data in a temporary storage cache and writing the loaded data into the EEPROM. At the same time that the low voltage level is detected during a write sequence, any load or write operation then in progress is aborted. The brownout detector is intentionally left disabled or in a sleep mode during any read mode or standby mode since there is no jeopardy of corrupting the EEPROM memory during those times.

US Patent:

53633342, Nov 8, 1994

Filed:

Apr 10, 1993

Appl. No.:

8/041068

Inventors:

Samuel E. Alexander - Gilbert AZ
Richard J. Fisher - Phoenix AZ
Kent D. Hewitt - Tempe AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 700

US Classification:

365218

Abstract:

An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

US Patent:

43227953, Mar 30, 1982

Filed:

Jan 24, 1980

Appl. No.:

6/114854

Inventors:

Ronald E. Lange - Phoenix AZ
Richard J. Fisher - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 930

US Classification:

364200

Abstract:

An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which to store data retrieved from main memory upon a cache miss. A duplicate directory arrangement is also disclosed for selective clearing of the cache in multiprocessor systems where data in a cache becomes obsolete by virtue of a change made to the corresponding data in main memory by another processor. The advantage of higher overall speed for CPU operations is achieved because of the higher hit ratio provided by the disclosed arrangement. In the preferred embodiment, the cache utilizes: a cache store for storing data; primary and duplicate directories for identifying the data stored in the cache; a full/empty array to mark the status of the storage locations; a least recently used array to indicate where incoming data should be stored; and a control means to orchestrate all these elements.