Richard M Jacobs

US Patent:

42401968, Dec 23, 1980

Filed:

Dec 29, 1978

Appl. No.:

5/974337

Inventors:

Richard M. Jacobs - Allentown PA
Ashok K. Sinha - New Providence NJ

Assignee:

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

International Classification:

B01J 1700

US Classification:

29578

Abstract:

In a two-level overlapping polysilicon device even the slightest amount of undercutting of an oxide layer (12) which underlies a first polysilicon layer (14) can lead to unacceptably low breakdown voltages in the device. In accordance with the invention, the first polysilicon and oxide layers of an LSI MOS wafer are defined as usual. But then the standard fabrication process is modified to etch the first polysilicon layer back beyond the edge of the oxide undercut. Subsequently, the structure is reoxidized and a second polysilicon layer (22) deposited and patterned. The modified process is characterized by the absence of any oxide thinning between the first and second polysilicon layers or between the second polysilicon layer and the substrate (10) of the device. As a result, voltage breakdown problems in the individual chips of the wafer are thereby greatly reduced and the yield of the wafer significantly increased.