Richard M Lienau

US Patent:

6545908, Apr 8, 2003

Filed:

Oct 18, 2000

Appl. No.:

09/691313

Inventors:

Richard M. Lienau - Pecos NM

Assignee:

Pageant Technologies, Inc.
Estancia Limited

International Classification:

G11C 1118

US Classification:

365170, 365158, 365171

Abstract:

A nonvolatile ferromagnetic RAM device which is capable of reading the data stored in each magnet quickly and efficiently utilizing a minimal number of components. Specifically there is a nonvolatile ferromagnetic RAM which is capable of reading the data stored in each magnetic bit. The ferromagnetic memory cell, comprising of a base ( ) that is oriented in a horizontal plane. There is also a bit ( ), made of a ferromagnetic material, having: a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height. Additionally, there is a sense line ( ), positioned proximate the bit ( ) sufficient to detect the directed polarity of the bit; and a write line ( ), positioned proximate the bit sufficient to direct the polarity of the bit. Additionally, there is a detector, coupled to the sense line; and a sample drive line ( ), positioned proximate the bit ( ) to transmit an electric pulse that will increase the directed polarity of the bit sufficient to induce a wave into the sense line that can be detected by the detector.

US Patent:

6680877, Jan 20, 2004

Filed:

Jan 24, 2003

Appl. No.:

10/350521

Inventors:

Richard M. Lienau - Pecos NM 87552

International Classification:

G04C 1900

US Classification:

368205, 368 10, 368 79, 368 82, 368223, 33269, 33270

Abstract:

A solar counter to provide an accurate way of measuring the middle of the night or another selected fraction of the day or night. The solar counter activates an electronic event when it has finished counting down. For example, a lamp can be turned off half way through the dark part of the night. This process is extremely accurate, and adaptations of this concept can be used in the safety industry, irrigation, or in agriculture. One embodiment of this concept has a battery back-up circuit, but a substitute 50/60 Hz clock input frequency in the case of AC power loss can also be provided using an uninterruptible power supply (UPS).

US Patent:

6710624, Mar 23, 2004

Filed:

Sep 18, 2002

Appl. No.:

10/239226

Inventors:

Richard M. Lienau - Pecos NM 87552

International Classification:

H03K 738

US Classification:

326 40, 326 38, 326 46, 326 37

Abstract:

A programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data. It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shutdown. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating âwrite fatigueâ. The invention provides an integrated circuit, comprising a programmable OR array ( ), a programmable AND array ( ), coupled to the programmable OR array, and a macrocell output circuit ( ). The macrocell uniquely has a ferromagnetic bit ( ) and sensor ( ) coupled to store remnant output signal, and an output buffer ( ), coupled to output the remnant output signal upon receiving an output enable signal.

US Patent:

6711069, Mar 23, 2004

Filed:

Sep 19, 2002

Appl. No.:

10/239127

Inventors:

Richard M. Lienau - Pecos NM 87552

International Classification:

G11C 1604

US Classification:

36518905, 365205, 365154, 365145

Abstract:

The invention generally related to registers or flip-flop circuits. More particularly, the present invention refers to the use of non-volatile ferromagnetic memory cell to store binary data in a register or flip-flop circuit. It is an advantage of the invention to have a flip-flop with a ferromagnetic memory cell or bit to store data even when there is no power provided to the circuitry. Thus, saving power during operation of any associated circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, or eliminating âwrite fatigueâ. The invention provides a latching circuit, comprising an input line entering the latching circuit for receiving a signal, an output line, electrically coupled to the input line, for outputting the signal, and a ferromagnetic bit and sensor coupled between the input line and the output line, to store a form of the signal in the ferromagnetic bit even when power has been suspended to the latching circuit.

US Patent:

6864711, Mar 8, 2005

Filed:

Jan 20, 2001

Appl. No.:

10/239133

Inventors:

Richard M. Lienau - Pecos NM, US

International Classification:

H03K007/38

US Classification:

326 41, 326 38, 326 82

Abstract:

A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array.

US Patent:

6873546, Mar 29, 2005

Filed:

Mar 8, 2001

Appl. No.:

10/239377

Inventors:

Richard M. Lienau - Pecos NM, US

International Classification:

G11C011/14

US Classification:

365171, 365173

Abstract:

A ferromagnetic memory cell is disclosed. The cell includes a bit (), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line () coupled to a first portion of the bit (), to feed a current into the bit (). A sense conductor () is coupled to a second portion of the bit (), to receive the current from the bit (). The current conducted through the bit () is responsive to the polarity of the bit (). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (). In this method, a bit () is provided that is made of ferromagnetic material and has a remnant polarity. An input current () is fed into the bit () through a read drive line () coupled to a first portion of the bit (). An output current () is received from the bit () through a sense conductor () coupled to a second portion of the bit (). The current conducted through the bit () is responsive to the polarity of the bit ().

US Patent:

7023727, Apr 4, 2006

Filed:

Jun 15, 2001

Appl. No.:

10/258289

Inventors:

Richard M. Lienau - Pecos NM, US
James Craig Stephenson - Salt Lake City UT, US

Assignee:

Pageant Technologies, Inc. - Toronto
Estancia Limited - Providenciales

International Classification:

G11C 11/14

US Classification:

365171, 365145, 365158

Abstract:

A ferromagnetic memory cell is disclosed having a base (), oriented in a horizontal plane, a bit (), made of a ferromagnetic material, and a sense/write line (), positioned proximate the bit () sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit () has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.

US Patent:

7123050, Oct 17, 2006

Filed:

Jan 18, 2005

Appl. No.:

11/037696

Inventors:

Richard M. Lienau - Pecos NM, US

International Classification:

H03K 19/177

US Classification:

326 38, 326 41

Abstract:

A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array.