Richard A List

US Patent:

6706584, Mar 16, 2004

Filed:

Jun 29, 2001

Appl. No.:

09/895362

Inventors:

Richard Scott List - Beaverton OR
Bruce A. Block - Portland OR
Mark T. Bohr - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218242

US Classification:

438239, 438250, 438253, 438612, 3613014, 3613062

Abstract:

A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

US Patent:

6737699, May 18, 2004

Filed:

Jun 27, 2002

Appl. No.:

10/185798

Inventors:

Bruce A. Block - Portland OR
Richard Scott List - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G 27108

US Classification:

257306, 257308, 257309

Abstract:

An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

US Patent:

6737728, May 18, 2004

Filed:

Oct 12, 2000

Appl. No.:

09/687906

Inventors:

Bruce A. Block - Portland OR
Richard Scott List - Beaverton OR
Ruitao Zhang - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27108

US Classification:

257532, 257296

Abstract:

On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

US Patent:

6800928, Oct 5, 2004

Filed:

May 28, 1998

Appl. No.:

09/087234

Inventors:

Wei William Lee - Plano TX
Richard Scott List - Beaverton OR
Changming Jin - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2358

US Classification:

257632, 257638, 257644, 257650

Abstract:

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).

US Patent:

6888716, May 3, 2005

Filed:

Jan 28, 2004

Appl. No.:

10/767559

Inventors:

Richard Scott List - Beaverton OR, US
Bruce A. Block - Portland OR, US
Mark T. Bohr - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G004/228

US Classification:

3613062, 3023061, 3023014, 302307, 3023211, 3023215, 438240, 438250, 438253, 438256, 257532, 257295, 257296

Abstract:

A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

US Patent:

7033882, Apr 25, 2006

Filed:

Jan 15, 2004

Appl. No.:

10/760080

Inventors:

Bruce A. Block - Portland OR, US
Richard Scott List - Beaverton OR, US
Ruitao Zhang - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/108
H01L 29/76
H01L 29/94
H01L 31/119
H01L 21/8242

US Classification:

438238, 438244, 438250, 438 3

Abstract:

On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

US Patent:

7138678, Nov 21, 2006

Filed:

Jan 27, 2004

Appl. No.:

10/766578

Inventors:

Bruce A. Block - Portland OR, US
Richard Scott List - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

257306, 257309, 257305

Abstract:

An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

US Patent:

7256089, Aug 14, 2007

Filed:

Sep 24, 2001

Appl. No.:

09/962786

Inventors:

Richard Scott List - Beaverton OR, US
Bruce A. Block - Portland OR, US
Ruitao Zhang - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8242
H01L 21/20

US Classification:

438253, 438240, 438396, 438648

Abstract:

An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.