Richard James O'Brien

US Patent:

7831490, Nov 9, 2010

Filed:

Feb 26, 2004

Appl. No.:

10/786023

Inventors:

Franco Modigliani - Cambridge MA, US
Serena Modigliani, legal representative - Cambridge MA, US
Richard James O'Brien - Lisle IL, US
Francis M. Vitagliano - Boston MA, US

Assignee:

Payment Pathways, Inc. - Chicago IL

International Classification:

G06Q 40/10

US Classification:

705 35

Abstract:

The present invention relates to a central (root) directory and/or network of directories to linked credit accounts. Each linked credit account accepts, or is responsive to incoming payments or credits, without the need for access numbers, account numbers, routing numbers, or the like. The payment/deposit account may be set up as a deposit only account (e. g. , it cannot pay out or be debited in the traditional sense). In this way, it can be effective in eliminating many of the security requirements of a traditional financial account.

US Patent:

D4162080, Nov 9, 1999

Filed:

Jul 2, 1998

Appl. No.:

D/090257

Inventors:

Michael D. Arney - Needham MA
David P. Chastain - Acton MA
Joseph R. Geringer - Melrose MA
Richard O'Brien - Waltham MA
John C. Costello - Wellesley MA
Ronald G. Wood - Mechanicsville VA
Kevin R. Young - Brighton MA

Assignee:

AMF Bowling Inc. - Mechanicsville VA

International Classification:

2101

US Classification:

D10 461

US Patent:

46213112, Nov 4, 1986

Filed:

Feb 6, 1985

Appl. No.:

6/698799

Inventors:

Richard A. O'Brien - Newton MA

Assignee:

Stevens-Arnold, Inc. - Boston MA

International Classification:

H02M 3335

US Classification:

363 21

Abstract:

A pulse-width modulation, switching DC-to-DC convertor uses positive feedback to combine the conventional comparator and state latch functions. The combined comparator/latch circuit reduces propagation delays through the circuitry and allows operation at higher frequencies. In place of the conventional serially-connected comparator, latch and output transistor, a high-speed comparator is modified by using positive feedback to convert it into a latching comparator. The duty cycle of the output transistor is controlled by the logical combination of the output of an internal oscillator and the output of the latching comparator. The latching comparator is controlled by an error signal and a signal representative of the current running through the output transistor thereby eliminating the usual ramp generation circuitry.