Richard B O'Brien

US Patent:

20090218997, Sep 3, 2009

Filed:

Feb 29, 2008

Appl. No.:

12/040397

Inventors:

George M. Hey - San Jose CA, US
John Chiang-Yung Lee - Palo Alto CA, US
Richard A. O'Brien - Livermore CA, US

International Classification:

G05F 1/10

US Classification:

323273

Abstract:

In one embodiment, a current limiter is configured to limit current drawn from a main power supply to a maximum value. A load device is coupled with an output of the current limiter. The load device is configured to periodically draw a first current during operation. The maximum value is below a value of the first current. A charge storage device is coupled with the load device. The charge storage device is configured to supply additional current to the load device to satisfy the first current value. A linear voltage regulator is coupled between the charge storage device and the load device.

US Patent:

20200196448, Jun 18, 2020

Filed:

Dec 17, 2018

Appl. No.:

16/222913

Inventors:

- San Jose CA, US
Kan Seto - Saratoga CA, US
Straty Argyrakis - San Jose CA, US
Joel Richard Goergen - Soulsbyville CA, US
Paul Lachlan Mantiply - Palo Alto CA, US
Richard Anthony O'Brien - Livermore CA, US

Assignee:

CISCO TECHNOLOGY, INC. - San Jose CA

International Classification:

H05K 1/14
H05K 1/18
H05K 1/02
H05K 1/11

Abstract:

In one embodiment, an apparatus generally comprises a power delivery board for integration with a printed circuit board, the power delivery board comprising a power plane for delivering power from a voltage regulator module to an application specific integrated circuit (ASIC) mounted on a first side of the printed circuit board. The power plane in the power delivery board interconnects with power vias in the power delivery board for vertical alignment with the ASIC through power vias in the printed circuit board to electrically couple the voltage regulator module and the ASIC when the power delivery board is mounted on a second side of the printed circuit board.