Richard H Pierson

US Patent:

20050023556, Feb 3, 2005

Filed:

Jul 30, 2003

Appl. No.:

10/632052

Inventors:

James Li - San Diego CA, US
Richard Pierson - Thousand Oaks CA, US
Berinder Brar - Newbury Park CA, US
John Higgins - Westlake Village CA, US

International Classification:

H01L029/76
H01L021/8249

US Classification:

257197000, 438235000

Abstract:

A BJT device configuration includes an emitter finger and via arrangement which reduces emitter finger width, and is particularly suitable for use with compound semiconductor-based devices. Each emitter finger includes a cross-shaped metal contact which provides an emitter contact; each contact comprises two perpendicular arms which intersect at a central area. A via through an inter-level dielectric layer provides access to the emitter contact; the via is square-shaped, centered over the center point of the central area, and oriented at a 45 angle to the arms. This allows the via size to be equal to or greater than the minimum process dimension, while allowing the width of the emitter finger to be as narrow as possible with the alignment tolerances still being met.

US Patent:

20050023643, Feb 3, 2005

Filed:

Jul 30, 2003

Appl. No.:

10/631380

Inventors:

James Li - San Diego CA, US
Richard Pierson - Thousand Oaks CA, US
Berinder Brar - Newbury Park CA, US
John Higgins - Westlake Village CA, US

International Classification:

H01L027/082

US Classification:

257565000

Abstract:

A bipolar junction transistor (BJT) requires the fabrication of a BJT structure and of a support post which is adjacent to, but physically and electrically isolated from, the BJT structure. The BJT structure includes a semi-insulating substrate, a subcollector, a collector, a base, and an emitter. Metal contacts are formed on the subcollector and emitter to provide collector and emitter terminals. Contact to the structure's base is accomplished with a metal contact which extends from the top of the support post to the edge of the base nearest the support post. The contact bridges the physical and electrical separation between the support post and the base and provides a base terminal for the device. The base contact need extend over the edge of the base by no more than the transfer length associated with the fabrication process. This results in the smaller base contact area over the collector than would otherwise be necessary, and a consequent reduction in base-collector capacitance. The invention is particularly useful when forming heterojunction bipolar transistors (HBTs), built on a compound semiconductor substrate such as indium phosphide (InP).

US Patent:

52508269, Oct 5, 1993

Filed:

Sep 23, 1992

Appl. No.:

7/949901

Inventors:

Peter M. Asbeck - San Diego CA
Richard L. Pierson - Thousand Oaks CA

Assignee:

Rockwell International Corporation - Seal Beach CA

International Classification:

H01L 2972

US Classification:

257273

Abstract:

A III-V compound planar HBT-FET device integrates field effect transistors (FETs) with heterojunction bipolar transistors (HBTs) formed on the same semiconductor substrate. An HBT fabricated on the substrate includes a collector, a base, and an emitter. The HBT emitter comprises a lightly doped layer of a first conductivity type deposited atop a heavily doped base layer of a second conductivity type, a lightly doped emitter cap layer of the first conductivity type deposited atop the emitter layer, and a heavily doped emitter contact layer of the first conductivity type deposited atop the emitter cap layer. A FET, isolated from the HBT by areas of ion implantation, is formed in the layers of material deposited during fabrication of the HBT. The FET has a source and a drain formed in the heavily doped emitter contact layer, a gate recess etched in the emitter contact layer between the source and drain, and a Schottky gate metal contact deposited on the lightly doped emitter cap layer exposed in the gate recess. A back gate electrode can be deposited on the base layer to form a dual-gate FET comprising a front gate MESFET and a back gate junction FET.