Richard R Pierson

US Patent:

6563145, May 13, 2003

Filed:

Dec 29, 1999

Appl. No.:

09/474624

Inventors:

Charles E. Chang - Newbury Park CA 91320
Richard L. Pierson - Thousand Oaks CA 91360
Peter J. Zampardi - Westlake Village CA 91361
Peter M. Asbeck - San Diego CA 92130

International Classification:

H01L 29739

US Classification:

257197, 257200, 438 35, 438235, 438342, 438796

Abstract:

A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e. g. , GaAs), and a narrow bandgap collector region (e. g. , InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

US Patent:

6906359, Jun 14, 2005

Filed:

Oct 22, 2003

Appl. No.:

10/692134

Inventors:

Peter J. Zampardi - Newbury Park CA, US
Richard Pierson - Thousand Oaks CA, US

Assignee:

Skyworks Solutions, Inc. - Irvine CA

International Classification:

H01L031/0328

US Classification:

257197, 257192, 257 20, 257 24, 257272, 257273, 257274

Abstract:

According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch stop layer, where the first segment of the etch stop layer comprises InGaP. The BiFET further comprises a FET situated over the substrate, where the FET comprises source and drain regions, where a second segment of the etch stop layer is situated under the source and drain regions, and where the second segment of the etch stop layer comprises InGaP. The FET further comprises a semiconductor layer of a second type situated under the second segment of the etch stop layer. The etch stop layer increases linearity of the FET and does not degrade electron current flow in the HBT.

US Patent:

8598857, Dec 3, 2013

Filed:

Dec 11, 2008

Appl. No.:

12/333003

Inventors:

Richard Pierson - Newport Beach CA, US
Scott Southwell - Seal Beach CA, US
Benjamim Tang - Rancho Palos Verdes CA, US
Timothy M. Ng - Monterey Park CA, US
Jinghong Guo - Torrance CA, US
Kenneth A. Ostrom - Palos Verdes Estates CA, US

Assignee:

Infineon Technologies Austria AG - Villach

International Classification:

G05F 1/575

US Classification:

323283, 323272, 323284

Abstract:

Methods and apparatus for a multiphase power regulator according various aspects of the present invention operate in conjunction with an active transient response (ATR) system for applying a correction signal to a multiphase pulse width modulator. In the event of a transient, the ATR system may adjust the output of the pulse width modulator to quickly respond to load requirements. The output may be modified by adding pulses, blanking pulses, advancing pulses, and scaling pulses to one or more phases.

US Patent:

20030151046, Aug 14, 2003

Filed:

Feb 14, 2002

Appl. No.:

10/075758

Inventors:

Berinder Brar - Newbury Park CA, US
Richard Pierson - Thousand Oaks CA, US
James Li - Thousand Oaks CA, US
John Higgins - Westlake Village CA, US

Assignee:

INNOVATIVE TECHNOLOGY LICENSING, LLC

International Classification:

H01L023/58

US Classification:

257/048000

Abstract:

Test probe pads are located lateral to, and spaced from, the emitter, base or collector region of a bipolar transistor, preferably on separate pedestals, and connected to their respective transistor regions by air bridges. The probe pads, transistor contacts and air bridges are preferably formed as common metallizations. In the case of an HBT, a gap in the subcollector below the air bridges insulates the test transistor from capacitor loading by the probe pads. The test transistors can be used to characterize both themselves and functional circuit transistors fabricated with the same process on the same wafer by testing at an intermediate stage of manufacture, thus allowing wafers to be discarded without completing the manufacture if their transistors do not meet specifications.

US Patent:

20030151066, Aug 14, 2003

Filed:

Feb 14, 2002

Appl. No.:

10/075428

Inventors:

Richard Pierson - Thousand Oaks CA, US
James Li - Thousand Oaks CA, US
Berinder Brar - Newbury Park CA, US
John Higgins - Westlake Village CA, US

Assignee:

Rockwell Technologies, LLC

International Classification:

H01L031/0328
H01L031/0336
H01L031/072
H01L031/109

US Classification:

257/197000

Abstract:

A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

US Patent:

20030197193, Oct 23, 2003

Filed:

Jan 27, 2003

Appl. No.:

10/353208

Inventors:

Richard Pierson - Thousand Oaks CA, US
James Li - Thousand Oaks CA, US
Berinder Brar - Newbury Park CA, US
John Higgins - Westlake Village CA, US

Assignee:

Innovative Technology Licensing, LLC

International Classification:

H01L031/0328

US Classification:

257/197000

Abstract:

A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

US Patent:

20040061128, Apr 1, 2004

Filed:

Sep 26, 2002

Appl. No.:

10/256042

Inventors:

Richard Pierson - Thousand Oaks CA, US
James Li - San Diego CA, US
Berinder Brar - Newbury Park CA, US
John Higgins - Westlake Village CA, US

Assignee:

Innovative Technology Licensing, LLC

International Classification:

H01L031/0328

US Classification:

257/183000

Abstract:

A heterojunction bipolar transistor (HBT) is disclosed that includes successive emitter, base and collector and sub-collector epitaxial layers and emitter, base and collector contact metals contacting the emitter, base and sub-collector layers respectively. A passivation material is included that covers the uncovered portions of the layers and covers substantially all of the contact metals. The passivation material has a planar surface and a portion of each of the contact metals protrudes from the surface. Planar metals are included on the planar surface, each being isolated from the others and in electrical contact with a respective contact metal. A method for fabricating an HBT is also disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locations for contact metals and emitter, base and contact metals are deposited on the emitter, base and sub-collector epitaxial layers, respectively. A self-alignment material is deposited on the surface of the substrate around the epitaxial layers and a planarization material is deposited on and covers the top surface of the HBT. The planarization material is then etched so it has a planar surface about the same level as the surface of the self-alignment material and the contact metals protrude from the planar surface. The planar metals are then deposited over the protruding portions of the contact metals.

US Patent:

20050023556, Feb 3, 2005

Filed:

Jul 30, 2003

Appl. No.:

10/632052

Inventors:

James Li - San Diego CA, US
Richard Pierson - Thousand Oaks CA, US
Berinder Brar - Newbury Park CA, US
John Higgins - Westlake Village CA, US

International Classification:

H01L029/76
H01L021/8249

US Classification:

257197000, 438235000

Abstract:

A BJT device configuration includes an emitter finger and via arrangement which reduces emitter finger width, and is particularly suitable for use with compound semiconductor-based devices. Each emitter finger includes a cross-shaped metal contact which provides an emitter contact; each contact comprises two perpendicular arms which intersect at a central area. A via through an inter-level dielectric layer provides access to the emitter contact; the via is square-shaped, centered over the center point of the central area, and oriented at a 45 angle to the arms. This allows the via size to be equal to or greater than the minimum process dimension, while allowing the width of the emitter finger to be as narrow as possible with the alignment tolerances still being met.