Richard Stephen Swanson

US Patent:

7468485, Dec 23, 2008

Filed:

Aug 11, 2005

Appl. No.:

11/201817

Inventors:

Richard M. Swanson - Los Altos CA, US

Assignee:

Sunpower Corporation - San Jose CA

International Classification:

H01L 25/00

US Classification:

136243

Abstract:

In one embodiment, a back side contact solar cell includes a tunnel oxide layer formed on a back side of a substrate. A polysilicon layer is formed on the tunnel oxide layer, and dopant sources are formed on the polysilicon layer. Dopants from the dopant sources are diffused into the polysilicon layer to form p-type and n-type regions therein. The p-type and n-type regions form p-n junctions that, among other advantages, allow for relatively high conversion efficiency.

US Patent:

7554031, Jun 30, 2009

Filed:

Aug 22, 2005

Appl. No.:

11/210213

Inventors:

Richard M. Swanson - Los Altos CA, US
Denis De Ceuster - Woodside CA, US
Vikas Desai - Cupertino CA, US
Douglas H. Rose - Mt. View CA, US
David D. Smith - San Jose CA, US
Neil Kaminar - Boulder Creek CA, US

Assignee:

Sunpower Corporation - San Jose CA

International Classification:

H01L 31/00

US Classification:

136261, 136251, 136259, 136256

Abstract:

In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell.

US Patent:

7633006, Dec 15, 2009

Filed:

Nov 18, 2008

Appl. No.:

12/272914

Inventors:

Richard M. Swanson - Los Altos Hills CA, US

Assignee:

Sunpower Corporation - San Jose CA

International Classification:

H01L 31/00

US Classification:

136258, 136243, 136261

Abstract:

In one embodiment, a back side contact solar cell includes a tunnel oxide layer formed on a back side of a substrate. A polysilicon layer is formed on the tunnel oxide layer, and dopant sources are formed on the polysilicon layer. Dopants from the dopant sources are diffused into the polysilicon layer to form p-type and n-type regions therein. The p-type and n-type regions form p-n junctions that, among other advantages, allow for relatively high conversion efficiency.

US Patent:

7705237, Apr 27, 2010

Filed:

Nov 27, 2006

Appl. No.:

11/563548

Inventors:

Richard M. Swanson - Los Altos CA, US

Assignee:

Sunpower Corporation - San Jose CA

International Classification:

H01L 31/028
H01L 31/06

US Classification:

136261, 136256, 136258, 136252, 136243, 438 57

Abstract:

A silicon solar cell having a silicon substrate includes p-type and n-type emitters on a surface of the substrate, the emitters being doped nano-particles of silicon. To reduce high interface recombination at the substrate surface, the nano-particle emitters are preferably formed over a thin interfacial tunnel oxide layer on the surface of the substrate.

US Patent:

7786375, Aug 31, 2010

Filed:

Jun 3, 2009

Appl. No.:

12/477796

Inventors:

Richard M. Swanson - Los Altos Hills CA, US
Denis De Ceuster - Woodside CA, US
Vikas Desai - Cupertino CA, US
Douglas H. Rose - San Jose CA, US
David D. Smith - San Jose CA, US
Neil Kaminar - Santa Cruz CA, US

Assignee:

SunPower Corporation - San Jose CA

International Classification:

H03H 5/10
H01L 31/00

US Classification:

136252, 323369

Abstract:

In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell.

US Patent:

7820475, Oct 26, 2010

Filed:

Dec 20, 2006

Appl. No.:

11/643743

Inventors:

Denis De Ceuster - Woodside CA, US
Peter John Cousins - Muntinlupa, PH
Richard M. Swanson - Los Altos CA, US
Jane E. Manning - Woodside CA, US

Assignee:

Sunpower Corporation - San Jose CA

International Classification:

H01L 21/225
H01L 31/0224

US Classification:

438 98, 438 71, 438 87, 257448, 257457, 257E31119, 257E31124, 257E3113, 257E21145, 136256, 136255

Abstract:

In one embodiment, active diffusion junctions of a solar cell are formed by diffusing dopants from dopant sources selectively deposited on the back side of a wafer. The dopant sources may be selectively deposited using a printing method, for example. Multiple dopant sources may be employed to form active diffusion regions of varying doping levels. For example, three or four active diffusion regions may be fabricated to optimize the silicon/dielectric, silicon/metal, or both interfaces of a solar cell. The front side of the wafer may be textured prior to forming the dopant sources using a texturing process that minimizes removal of wafer material. Openings to allow metal gridlines to be connected to the active diffusion junctions may be formed using a self-aligned contact opening etch process to minimize the effects of misalignments.

US Patent:

8058905, Nov 15, 2011

Filed:

Jan 31, 2009

Appl. No.:

12/363722

Inventors:

Matthew H. Klein - Redwood City CA, US
Richard W. Swanson - San Jose CA, US
Trevor J. Bauer - Boulder CO, US
Steven P. Young - Boulder CO, US
Andy DeBaets - Cupertino CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/00
H03K 3/356

US Classification:

326 93, 327208

Abstract:

Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.

US Patent:

8163638, Apr 24, 2012

Filed:

Sep 15, 2010

Appl. No.:

12/883045

Inventors:

Denis De Ceuster - Woodside CA, US
Peter John Cousins - Menlo Park CA, US
Richard M. Swanson - Los Altos Hills CA, US
Jane E. Manning - Woodside CA, US

Assignee:

SunPower Corporation - San Jose CA

International Classification:

H01L 21/225
H01L 31/0224

US Classification:

438558, 438 71, 438 87, 438 98, 257448, 257457, 257E31119, 257E31124, 257E3113, 257E21145, 257E21469, 136256, 136255

Abstract:

In one embodiment, active diffusion junctions of a solar cell are formed by diffusing dopants from dopant sources selectively deposited on the back side of a wafer. The dopant sources may be selectively deposited using a printing method, for example. Multiple dopant sources may be employed to form active diffusion regions of varying doping levels. For example, three or four active diffusion regions may be fabricated to optimize the silicon/dielectric, silicon/metal, or both interfaces of a solar cell. The front side of the wafer may be textured prior to forming the dopant sources using a texturing process that minimizes removal of wafer material. Openings to allow metal gridlines to be connected to the active diffusion junctions may be formed using a self-aligned contact opening etch process to minimize the effects of misalignments.