Richard S Terrill

US Patent:

6384630, May 7, 2002

Filed:

Jan 12, 2001

Appl. No.:

09/760231

Inventors:

Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Fremont CA
Kerry Veenstra - San Jose CA
Andreas Papaliolios - Sunnyvale CA
Chiakang Sung - Milpitas CA
Richard Shaw Terrill - Santa Clara CA
Rina Raman - Los Altos CA
Robert Richard Noel Bielby - Pleasonton CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39, 711103, 711100, 711165, 711170

Abstract:

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

US Patent:

6636936, Oct 21, 2003

Filed:

Apr 6, 2000

Appl. No.:

09/544379

Inventors:

Richard Shaw Terrill - Sunnyvale CA
Robert Richard Noel Bielby - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1300

US Classification:

711103, 711100, 711165, 711170

Abstract:

Apparatus and methods for configuring a plurality of programmable logic devices which include the steps of providing a source of configuration data and transferring the configuration data directly from the source to each of the programmable logic devices. In some embodiments, the methods permit the programmable logic devices to configure themselves without the intervention of an intelligent host such as a CPU, a microcontroller, or other types of intelligent logic. In other embodiments, configuration data files are used in conjunction with an intelligent host to configure the programmable logic devices. Configuration is performed at power-up or, alternatively, under user or software control.

US Patent:

6642064, Nov 4, 2003

Filed:

Mar 3, 1997

Appl. No.:

08/810567

Inventors:

Richard S. Terrill - Sunnyvale CA
Donald F. Faria - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3126

US Classification:

438 15

Abstract:

A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The prepackaged PLDs and the ability to use the substrate as a burn-in vehicle for the FPIC die results in reliable and reworkable assembly process with minimized yield loss.

US Patent:

20130214814, Aug 22, 2013

Filed:

Mar 14, 2013

Appl. No.:

13/827902

Inventors:

WAVE SEMICONDUCTOR, INC. - , US
Richard Shaw Terrill - San Jose CA, US

Assignee:

WAVE SEMICONDUCTOR, INC. - Sunnyvale CA

International Classification:

H03K 19/094

US Classification:

326 36

Abstract:

A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state.

US Patent:

56422628, Jun 24, 1997

Filed:

Feb 23, 1995

Appl. No.:

8/393576

Inventors:

Richard S. Terrill - Sunnyvale CA
Donald F. Faria - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H05K 702
H05K 116

US Classification:

361783

Abstract:

A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The input/output terminals of the PLDs are interconnected with the FPIC die in a scrambled fashion to reduce signal skew.

US Patent:

59784768, Nov 2, 1999

Filed:

Aug 11, 1997

Appl. No.:

8/908084

Inventors:

Scott Redman - Fremont CA
Dennis Mak - Mountain View CA
Richard Terrill - Santa Clara CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04L 932
H04L 900

US Classification:

380 4

Abstract:

A computerized system restricts full revelation of certain information to a user, while also performing limited processing of the information for the user for evaluation. The information is encrypted and therefore may be widely distributed without fear of revelation. An authorization code from the user specifies the type(s) of processing that are permitted, wherein different types of processing produce different type(s) of output that reveal to different degrees the information. The type(s) of output include output which represent more than mere reproduction of the information. A particularly appropriate implementation of the present invention is in the area of Electronic Design Automation (EDA) for logic design.

US Patent:

55437303, Aug 6, 1996

Filed:

May 17, 1995

Appl. No.:

8/442801

Inventors:

Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Santa Clara CA
Kerry Veenstra - San Jose CA
Andreas Papaliolios - Sunnyvale CA
Chiakang Sung - Milpitas CA
Richard S. Terrill - Santa Clara CA
Rina Raman - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 38

Abstract:

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

US Patent:

61916080, Feb 20, 2001

Filed:

May 5, 1997

Appl. No.:

8/851250

Inventors:

Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Fremont CA
Kerry Veenstra - San Jose CA
Andreas Papaliolios - Sunnyvale CA
Chiakang Sung - Milpitas CA
Richard Shaw Terrill - Santa Clara CA
Rina Raman - Los Altos CA
Robert Richard Noel Bielby - Pleasanton CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 38

Abstract:

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.