Richard Rd Webb

US Patent:

6356624, Mar 12, 2002

Filed:

Aug 4, 1998

Appl. No.:

09/128579

Inventors:

Russell J. Apfel - Austin TX
Richard B. Webb - Austin TX
Walter S. Schopfer - Austin TX

Assignee:

Leserity, Inc. - Austin TX

International Classification:

H04M 322

US Classification:

379 2701, 379 2705, 379 2708, 37939901

Abstract:

A sensor capable of being coupled to a transmission line and monitoring a foreign voltage on the transmission line includes a voltage monitoring circuit. The voltage monitoring circuit is adapted to operate in a foreign voltage detection mode in response to receiving a first logic signal and a foreign voltage measurement mode in response to receiving a second logic signal. A method for operating a circuit to detect and measure a foreign voltage on a transmission line includes providing a first logic signal to configure the circuit to detect the foreign voltage. The foreign voltage is detected on the transmission line in the circuit. A second logic signal is provided to configure the circuit to measure the foreign voltage, and the foreign voltage is measured.

US Patent:

7511388, Mar 31, 2009

Filed:

Jun 6, 2006

Appl. No.:

11/448065

Inventors:

Richard B. Webb - Austin TX, US
D. Matthew Landry - Austin TX, US

Assignee:

Silicon Laboratories, Inc. - Austin TX

International Classification:

H02J 4/00
H02J 1/00
H02J 3/14

US Classification:

307 31, 307 39

Abstract:

A powered device includes a power supply input, a diode bridge, and a power loss detector. The power supply input is responsive to an external power source. The diode bridge has an input to receive at least one power supply input. The power loss detector includes an input responsive to the power supply input. The power loss detector is adapted to detect a power loss event and to initiate a power shutdown. In one embodiment, the powered device includes a load circuit to receive a power supply voltage from the diode bridge. The load circuit is responsive to the power loss detector to perform a power shutdown operation.

US Patent:

7541790, Jun 2, 2009

Filed:

Jun 9, 2006

Appl. No.:

11/450790

Inventors:

Walter S. Schopfer - Austin TX, US
Richard B. Webb - Austin TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

G05F 1/40

US Classification:

323282

Abstract:

In one embodiment, the present invention includes a regulator having a pulse width modulation (PWM) controller to generate a PWM control signal based on a voltage level of a load coupled to the regulator, a driver to provide a drive signal to a switching element of the regulator responsive to the PWM control signal, and a power saver coupled between the PWM controller and the driver to receive the PWM control signal and to output the PWM control signal to the driver at a reduced rate during an idle mode of the load.

US Patent:

7609494, Oct 27, 2009

Filed:

Jun 30, 2006

Appl. No.:

11/480328

Inventors:

Richard Bruce Webb - Austin TX, US

Assignee:

Silicon Laboratories, Inc. - Austin TX

International Classification:

H02H 3/20

US Classification:

361 56, 361 917

Abstract:

A powered device includes a voltage protection circuit, two outputs, a switch, and a snubber circuit. The two outputs of the integrated circuit may be coupled to an external transformer. The snubber circuit of the integrated circuit is responsive to the switch and is coupled with respect to the two outputs to direct energy from at least one of the two outputs to the voltage protection circuit.

US Patent:

7715165, May 11, 2010

Filed:

Jul 11, 2006

Appl. No.:

11/484449

Inventors:

John Gammel - Austin TX, US
Richard B. Webb - Austin TX, US
D. Matthew Landry - Austin TX, US

Assignee:

Silicon Laboratories, Inc. - Austin TX

International Classification:

H02H 3/20
H02H 9/04

US Classification:

361111, 361 56, 361 911

Abstract:

A powered device includes a first supply terminal, a second supply terminal, and at least one input pin coupled to the first supply terminal. The powered device further includes an external capacitor having a first terminal coupled to the first supply terminal, a switch coupled to the second supply terminal and coupled to a second terminal of the external capacitor, and power surge detection logic coupled to the switch. The external capacitor is charged in response to a detected power surge that exceeds a threshold.

US Patent:

7855445, Dec 21, 2010

Filed:

Apr 29, 2008

Appl. No.:

12/111341

Inventors:

D. Matthew Landry - Austin TX, US
Richard Webb - Austin TX, US

Assignee:

Silicon Laboratories, Inc. - Austin TX

International Classification:

H01L 23/02

US Classification:

257686, 257777, 438107

Abstract:

In a particular embodiment, a circuit device includes a first die coupled to a circuit substrate and having a substantially planar surface. The first die includes electrical contacts distributed on the substantially planar surface adjacent to at least three edges of the first die. The circuit device further includes a second die attached to the substantially planar surface of the first die. The second die is rotated by an offset angle about an axis relative to the first die. The offset angle is selected to allow horizontal and vertical access to the electrical contacts.

US Patent:

7932577, Apr 26, 2011

Filed:

Dec 31, 2007

Appl. No.:

11/967895

Inventors:

Richard Bruce Webb - Austin TX, US
William E. Moore - Round Rock TX, US

Assignee:

Silicon Laboratories, Inc. - Austin TX

International Classification:

H01L 27/08

US Classification:

257531, 257277, 257341, 257343, 257E21022

Abstract:

In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a body terminal. The method further includes depositing a plurality of metal contacts along a width of a gate terminal of the FET device and forming a wire trace to contact each of the plurality of metal contacts to reduce a gate resistance along the width of the gate terminal.

US Patent:

7970125, Jun 28, 2011

Filed:

Jun 15, 2006

Appl. No.:

11/453418

Inventors:

Russell J. Apfel - Austin TX, US
Richard B. Webb - Austin TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H04M 1/00
H04M 9/00

US Classification:

379413

Abstract:

In one embodiment, the present invention includes an operational amplifier having a first input to receive a first current formed of an input current and an offset current. A first MOSFET device having a gate terminal may be coupled to an output of the operational amplifier. An output stack including one or more cascoded devices to provide an output current corresponding to a gain of the operational amplifier may be coupled to a first terminal of the first MOSFET device. The operational amplifier may be used in various circuitry, such as a subscriber line interface circuit (SLIC).