Robert C Ayers

US Patent:

8576578, Nov 5, 2013

Filed:

Jun 27, 2011

Appl. No.:

13/170010

Inventors:

Robert L. Ayers - Durham NC, US
Michael L. Scollard - Raleigh NC, US
Heidi D. Williams - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 1/11
H05K 1/14

US Classification:

361794, 361748, 361799, 36167902

Abstract:

A robust printed circuit board (PCB) that includes at least two power layers that are used in providing power to components connected to the PCB. The power layers may be a power plane layer and a ground plane layer. The power plane layer is situated such that its edge is pulled back a second distance from the planar edge of the PCB. The ground plane layer is situated such that its edge is pulled back a first distance from the planar edge of the PCB. The second distance and the first distance are different, and as a result, the planar edges of the power plane layer and the ground plane layer respectively do not coincide.

US Patent:

20040083413, Apr 29, 2004

Filed:

Oct 29, 2002

Appl. No.:

10/282825

Inventors:

Robert Ayers - Durham NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R031/28

US Classification:

714/727000

Abstract:

An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.

US Patent:

20060156124, Jul 13, 2006

Filed:

Jan 19, 2006

Appl. No.:

11/337045

Inventors:

Robert Ayers - Durham NC, US

International Classification:

G01R 31/28

US Classification:

714727000

Abstract:

An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.

US Patent:

57605980, Jun 2, 1998

Filed:

Feb 12, 1996

Appl. No.:

8/599900

Inventors:

Robert Lee Ayers - Durham NC
Geoffrey B. Stephens - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3126

US Classification:

324765

Abstract:

A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

US Patent:

59398973, Aug 17, 1999

Filed:

Feb 11, 1998

Appl. No.:

9/022305

Inventors:

Robert Lee Ayers - Durham NC
Geoffrey B. Stephens - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 190948
H03K 1900

US Classification:

326 58

Abstract:

A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

US Patent:

43428924, Aug 3, 1982

Filed:

Aug 8, 1980

Appl. No.:

6/176499

Inventors:

Robert D. Ayers - Raleigh NC

Assignee:

Stackpole Components Company - Raleigh NC

International Classification:

H01H 126
H01H 1352

US Classification:

200159A

Abstract:

A keyswitch includes a tubular plunger with a body slidable vertically in an open-top housing that has a bottom wall supporting the lower end of a coil spring extending up around a pair of opposed upright spring contact strips, the lower ends of which extend through the bottom wall. The inside of the plunger is provided with a cross member that normally separates the upper ends of the contact strips, but permits them to engage each other when the plunger is pushed down. The contact strips are substantially identical. Each has at least two parallel slits extending downwardly from its upper end to form a plurality of narrow contact fingers beside a wider contact finger that is wide enough to be engaged by the narrow contact fingers of the opposing contact strip.

US Patent:

50381580, Aug 6, 1991

Filed:

Nov 13, 1989

Appl. No.:

7/435767

Inventors:

Robert W. Ayers - Olathe KS
Richard M. Kerbel - Shawnee KS

Assignee:

Applied Resources, Inc. - Overland Park KS

International Classification:

G01D 1506
H04N 123

US Classification:

3461531

Abstract:

A gray scale image poster printer reproduces a digitally stored bit map image on a printer using an electrostatic and magnetic toner to generate gray scale images by expanding each line of the original stored image into a plurality of subpixels along the horizontal scanning lines and by synchronizing the printing of the subpixel lines with a changing magnetic field that changes the amount of toner deposited in each subpixel.

US Patent:

43617433, Nov 30, 1982

Filed:

Mar 6, 1981

Appl. No.:

6/241243

Inventors:

Robert D. Ayers - Raleigh NC

Assignee:

Stackpole Components Company - Raleigh NC

International Classification:

H01H 1352
H01H 312

US Classification:

200153V

Abstract:

A hollow plunger is slidable vertically in a housing that has an open upper end, but its upward travel is limited to a predetermined elevated position, in which the lower end of the plunger body is spaced above the housing's bottom wall that holds a pair of opposed spring contact strips that extend below it to form terminals and that also converge upwardly inside the plunger and have upper ends urged toward engagement with each other. Loosely disposed inside the plunger is a shuttle provided with a cross member extending between the contact strips. The inside of the plunger is formed for supporting the shuttle while the plunger is held in its elevated position by a coil spring encircling the contact strips with the shuttle cross member spreading the upper ends of the contacts apart. After the plunger has been depressed a predetermined distance, it starts to move the shuttle downwardly with it. The inner side of each contact strip is provided with a projection extending from the point of engagement of the strip by the raised cross member downwardly a predetermined distance to hold the contacts apart until the descending cross member slides off the lower ends of the projections.