Robert W Barker

US Patent:

20070162268, Jul 12, 2007

Filed:

Jan 12, 2006

Appl. No.:

11/331565

Inventors:

Bhaskar Kota - San Jose CA, US
Paul Master - Sunnyvale CA, US
Robert Barker - San Jose CA, US
Robert Plunkett - Sunnyvale CA, US

International Classification:

G06F 17/50

US Classification:

703014000

Abstract:

A computing system and method are provided for algorithmic electronic system level design. An exemplary system comprises a plurality of databases for storing a plurality of functional models, a plurality of computational element models, and a plurality of hardware definition representations. An application design processor is adapted to perform a first functional simulation of an algorithm using a plurality of computational element architecture definitions to generate a first selection of a plurality of computational elements and corresponding control code for an implementation of the algorithm. A control and memory modeling processor is adapted to generate a plurality of flow transforms from the algorithm and to convert the plurality of flow transforms into the plurality of plurality of computational element models. A system simulation processor is adapted to convert the plurality of computational element models into the plurality of hardware definition representations and to perform a second functional simulation of the algorithm using the plurality of computational element models corresponding to the first selection and the corresponding control code.

US Patent:

46981047, Oct 6, 1987

Filed:

Mar 2, 1987

Appl. No.:

7/018769

Inventors:

Robert A. Barker - Mountain View CA
Chuang C. Tsai - San Jose CA
John C. Knights - Palo Alto CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H01L 21385

US Classification:

437141

Abstract:

A method of doping selected areas of semiconductor material in the fabrication of integrated circuit devices, including placing a semiconductor substrate in a glow discharge reactor, introducing reactant gases into the reactor, subjecting the reactant gases to a plasma discharge, depositing, upon the substrate, a dopant carrier layer comprising an amorphous semiconductor material having a predetermined dopant concentration, controlling the thickness of the dopant carrier layer, and driving the dopant atoms out of the amorphous semiconductor dopant carrier layer into the selected areas of the semiconductor substrate by means of a controlled elevated temperature anneal.