Robert L Berry

US Patent:

63287501, Dec 11, 2001

Filed:

Sep 6, 2000

Appl. No.:

9/655905

Inventors:

Robert Lawrence Berry - Kirkland WA
Matt Hefner - Puyallup WA
Tom Hiblar - Everett WA
Joseph Pearce - Seattle WA
Natalya Peskin - Redmond WA
Edward Wulfman - Woodinville WA

Assignee:

SciMed Life Systems, Inc. - Maple Grove MN

International Classification:

A61B 1732

US Classification:

606168

Abstract:

An ablation burr has a body provided with an inner circumferential rim and an outer circumferential rim that are concentric and spaced longitudinally by a selected distance along the length of the burr. The outer circumferential rim has a generally smooth convex outer surface that reduces damage to a vessel wall or stent A leading surface of the burr extends between the inner and outer circumferential rims in a substantially uniform, concave manner. An abrasive, for example, diamond grit, is provided on the leading surface. The burr is selectively rotated by a drive shaft, causing the abrasive leading surface of the burr to ablate unwanted deposits. If desired, a wire extends co-axially through the body such that a distal end of the wire extends out of the distal end of the burr. An abrasive tip may be coupled to the distal end of the wire, and is selectively rotated, to ablate unwanted deposits. The burr may be made of a compressible elastomeric material, to facilitate positioning the burr through restrictive openings, such as the coronary ostia.

US Patent:

45727651, Feb 25, 1986

Filed:

May 2, 1983

Appl. No.:

6/490622

Inventors:

Robert L. Berry - San Mateo CA

Assignee:

Fairchild Camera & Instrument Corporation - Mountain View CA

International Classification:

B44C 122
C03C 1500
C03C 2506

US Classification:

156643

Abstract:

A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 30 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 32 having etching characteristics different from the first layer 30 on the first layer 30, anisotropically etching the first layer 30 and the second layer 32 from all of the underlying integrated circuit structure 26 except for a desired region having a periphery which includes the narrow region, forming a coating 35 of smoothing material over all of the underlying integrated circuit structure 26 except for the first layer 30, and isotropically etching the first layer 30 to remove it from the surface of the underlying integrated circuit structure 26 to thereby define the narrow region 36. Use of the process to fabricate a compact bipolar transistor structure is also disclosed.

US Patent:

44352255, Mar 6, 1984

Filed:

May 11, 1981

Appl. No.:

6/262568

Inventors:

Jay A. Shideler - San Mateo CA
Robert L. Berry - Cupertino CA

Assignee:

Fairchild Camera & Instrument Corporation - Mountain View CA

International Classification:

H01L 2972
H01L 21225
H01L 2122

US Classification:

148 15

Abstract:

A lateral bipolar transistor having a base width of 0. 5 micron or less is made by forming a protective layer on an electrically insulating layer along a surface of a semiconductor body, forming an open space through the protective layer so as to define a guiding edge for it, introducing a first semiconductor dopant of a selected conductivity type into the body using the guiding edge to control the lateral extent of the first dopant, etching the insulating layer back under the protective layer a selected distance from the guiding edge, oxidizing material of the body exposed by the open space in the protective and insulating layers to form a composite electrically insulating region, removing the remainder of the protective layer, etching the insulating region sufficiently long to create an open space through it and thereby define another guiding edge, and introducing a second semiconductor dopant of the selected conductivity type into the body using this second guiding edge to control the lateral extent of the second dopant toward the first dopant and thereby to control the resulting base width.

US Patent:

20180350232, Dec 6, 2018

Filed:

May 30, 2018

Appl. No.:

15/993204

Inventors:

- Eindhoven, NL
Andrew LEWIS - Berkeley CA, US
Jane MACFARLANE - Oakland CA, US
Robert BERRY - Chicago IL, US

International Classification:

G08G 1/01
G06F 17/30
G06K 9/62

Abstract:

An approach is provided for next token prediction based on previously observed tokens. The approach involves receiving an observed time series of tokens, wherein each of the tokens represents an observed data pattern. The approach also involves adding a most recent token from the observed time series of tokens into a variable token set. The approach further involves processing a historical token set to determine a historical token sequence comprising the variable token set followed by a next token. The approach further involves recursively adding a next most recent token from the observed time series of tokens into the variable token set for processing until the next token following the variable token set in the determined historical token sequence is unique or meets a target number of possible predictions. The approach further involves presenting the next token as a predicted next token of the observed time series of tokens.