Robert B Blankenship

US Patent:

6681292, Jan 20, 2004

Filed:

Aug 27, 2001

Appl. No.:

09/940835

Inventors:

Kenneth C. Creta - Gig Harbor WA
Mike Bell - Beaverton OR
Robert George - Austin TX
Bradford B Congdon - Olympia WA
Robert Blankenship - Tacoma WA
Duane January - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711119, 711141, 711145, 711146, 709217

Abstract:

A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

US Patent:

6842827, Jan 11, 2005

Filed:

Jan 2, 2002

Appl. No.:

10/038996

Inventors:

Robert G. Blankenship - Tacoma WA, US
Matthew A. Lambert - Olympia WA, US
Tony S. Rand - Tacoma WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711141, 711146, 711137, 710 39, 710 40

Abstract:

A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

US Patent:

6842828, Jan 11, 2005

Filed:

Apr 30, 2002

Appl. No.:

10/135552

Inventors:

Robert G. Blankenship - Tacoma WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

711141

Abstract:

A cache coherency arrangement to enhance an upbound path for input-output interfaces is disclosed. Several embodiments may enhance upbound write bandwidth and buffer utilization. Some embodiments may comprise requesting content of a memory granule and merging the content with data associated with a write request for the memory granule prior to satisfaction of an ordering rule associated with the write request. Many embodiments may comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation and/or deadlock of transactions or of an input-output interface for transactions. Such embodiments may also comprise invalidating merged content of the memory granule. Further embodiments may comprise reverting the merged content to the data associated with the write request.

US Patent:

7089362, Aug 8, 2006

Filed:

Dec 27, 2001

Appl. No.:

10/035034

Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Robert Blankenship - Tacoma WA, US
Robert George - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711133, 711135, 711144, 711159, 711170

Abstract:

Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.

US Patent:

7165131, Jan 16, 2007

Filed:

Apr 27, 2004

Appl. No.:

10/833236

Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Aaron T. Spink - San Francisco CA, US
Robert G. Blankenship - Tacoma WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00
G06F 13/36
G06F 13/42

US Classification:

710100, 710 52, 710 5, 710113, 710158, 710310, 710309, 710316, 710105, 370401, 370252, 3703954

Abstract:

In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.

US Patent:

7210000, Apr 24, 2007

Filed:

Apr 27, 2004

Appl. No.:

10/832607

Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Robert G. Blankenship - Tacoma WA, US
Sridhar Muthrasanallur - Tumwater WA, US
Jasmin Ajanovic - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00
H03M 13/00

US Classification:

710316, 710106, 709238, 370356

Abstract:

In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.

US Patent:

8250435, Aug 21, 2012

Filed:

Sep 15, 2009

Appl. No.:

12/559953

Inventors:

Robert G. Blankenship - Tacoma WA, US
Dennis W. Brzezinski - Sunnyvale CA, US
Edwin F. Mendez Valverde - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714758, 714781

Abstract:

An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error.

US Patent:

7996572, Aug 9, 2011

Filed:

Jun 2, 2004

Appl. No.:

10/859891

Inventors:

Robert G. Blankenship - Tacoma WA, US
Robert J. Greiner - Beaverton WA, US
Herbert H. J. Hum - Portland OR, US
Kenneth C. Creta - Gig Harbor WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 7/38

US Classification:

710 5, 712 22

Abstract:

Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.