Robert L Blankenship

US Patent:

7546422, Jun 9, 2009

Filed:

Aug 28, 2002

Appl. No.:

10/231414

Inventors:

Robert T George - Austin TX, US
Mathew A Lambert - Olympia WA, US
Tony S Rand - Tacoma WA, US
Robert G Blankenship - Tacoma WA, US
Kenneth C Creta - Gig Harbor WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711145, 711146, 711141, 711129

Abstract:

A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

US Patent:

8046539, Oct 25, 2011

Filed:

Jun 5, 2009

Appl. No.:

12/479541

Inventors:

Robert T. George - Austin TX, US
Mathew A. Lambert - Olympia WA, US
Tony S. Rand - Tacoma WA, US
Robert G. Blankenship - Tacoma WA, US
Kenneth C. Creta - Gig Harbor WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711141, 711146, 711144, 711E12026

Abstract:

A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

US Patent:

20130007491, Jan 3, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/175794

Inventors:

VENKATRAMAN IYER - Austin TX, US
ROBERT G. BLANKENSHIP - Tacoma WA, US
DENNIS R. HALICKI - Hillsboro OR, US

International Classification:

G06F 1/32

US Classification:

713321

Abstract:

Methods and apparatus relating to enhanced interconnect link width modulation for power savings are described. In one embodiment, the width of a link is modified from a first width to a second width in response to a power management flit, while non-idle flits continue to be transmitted over the link after transmission of the power management flit. Other embodiments are also disclosed and claimed.

US Patent:

20130007502, Jan 3, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/175798

Inventors:

VENKATRAMAN IYER - Austin TX, US
ROBERT G. BLANKENSHIP - Tacoma WA, US
ALLEN J. BAUM - Palo Alto CA, US

International Classification:

G06F 11/20

US Classification:

714 3, 714E11071

Abstract:

Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.

US Patent:

20140006677, Jan 2, 2014

Filed:

Jun 29, 2012

Appl. No.:

13/537837

Inventors:

Venkatraman Iyer - Austin TX, US
Debendra Das Sharma - Saratoga CA, US
Robert G. Blankenship - Tacoma WA, US
Darren S. Jue - Sunnyvale CA, US

International Classification:

G06F 13/40

US Classification:

710316

Abstract:

Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.

US Patent:

20140215112, Jul 31, 2014

Filed:

Mar 15, 2013

Appl. No.:

13/976960

Inventors:

Venkatraman Iyer - Austin TX, US
Darren S. Jue - Sunnyvale CA, US
Robert G. Blankenship - Tacoma WA, US
Fulvio Spagna - San Jose CA, US
Ashish Gupta - Chandler AZ, US

International Classification:

G06F 13/42

US Classification:

710106

Abstract:

Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a predefined sequence on each of the lanes.

US Patent:

20140115207, Apr 24, 2014

Filed:

Mar 27, 2013

Appl. No.:

13/976937

Inventors:

Venkatraman Iyer - Austin TX, US
Darren S. Jue - Sunnyvale CA, US
Robert G. Blankenship - Tacoma WA, US
Fulvio Spagna - San Jose CA, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US

International Classification:

G06F 13/42

US Classification:

710105

Abstract:

A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

US Patent:

20140115374, Apr 24, 2014

Filed:

Mar 27, 2013

Appl. No.:

13/976927

Inventors:

Venkatraman Iyer - Austin TX, US
Darren S. Jue - Sunnyvale CA, US
Jeff Willey - Timnath CO, US
Robert G. Blankenship - Tacoma WA, US

International Classification:

G06F 1/12

US Classification:

713400

Abstract:

A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.