Robert T Brunner

US Patent:

56507607, Jul 22, 1997

Filed:

Nov 13, 1995

Appl. No.:

8/555469

Inventors:

Joginder S. Degun - Torrance CA
Robert A. Brunner - Redondo Beach CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01P 100
H01L 2310

US Classification:

333246

Abstract:

Microwave ports and low-frequency ports of a microwave enclosure are configured to realize high return losses and low insertion losses and suppress resonance modes below a predetermined microwave frequency. The microwave ports include microwave transmission lines which have first and second microstrip portions and a stripline portion which connects the first and second microstrip portions. The microwave transmission lines are positioned with the stripline portion received in a housing aperture. The low-frequency ports include a dielectric member and a plurality of metallic signal lines carried within the dielectric member. The dielectric member is relieved to expose inner and outer ends of the signal lines. The connector systems are received in housing apertures with metallic members positioned through the dielectric members and across the connector apertures to electrically partition the connector apertures into subapertures which each have a predetermined microwave cutoff frequency.

US Patent:

56131976, Mar 18, 1997

Filed:

Nov 3, 1994

Appl. No.:

8/334491

Inventors:

Wilbert B. Copeland - Los Angeles CA
Erik Soderburg - Redondo Beach CA
John Dunwoody - Long Beach CA
Robert Brunner - Redondo Beach CA
Keith Williams - Los Angeles CA

Assignee:

Hughes Aircraft Co. - Los Angeles CA

International Classification:

H04B 714

US Classification:

455 22

Abstract:

Input RF signals to a transponder, such as a communications satellite, are down converted to a lower intermediate frequency (IF) that is common for each different channel. The channel signals are all processed at the common IF, and then up converted to different respective transmission frequencies. This allows for a down conversion/signal processing/up conversion unit design that is the same for each channel (except for frequency and gain values), and facilitates the use of inexpensive available standard components as well as low bandwidth channel filters. An improved phase noise cancellation phase lock loop (PLL) is preferably used to generate tuning signals used in the up and down conversion processes. The PLL includes two loop mixers, with the down and up conversion mixing signals taken respectively from the inputs to the first and second loop mixers. The first and second loop mixers receive mixing signals at frequencies (T-R) and (T-IF-N. multidot.

US Patent:

57541183, May 19, 1998

Filed:

Mar 25, 1996

Appl. No.:

8/621608

Inventors:

Robert A. Brunner - Redondo Beach CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H04Q 1900
H03K 1780
H11C 1302
G01R 3108

US Classification:

34082579

Abstract:

A switch matrix having internal redundancy by combining outputs of two internal channels to form one single internally redundant channel. 1 by N, M by 1 and M by N switch matrices may be constructed using the principles of the present invention. Each input signal line is coupled between a signal input and a terminating resistor and each output signal line is coupled between a signal output and a terminating resistor. Switching nodes are formed that comprise an input line, a plurality of output lines, and a plurality of pairs of couplers that are respectively interconnected by way of respective switches used to select the input line and couple it to a respective output line. Pairs of output signal lines are connected to a single signal output to form internally redundant channels. The nodes may include a second serially coupled switch connected between the input and output couplers to provide redundancy if either one of the switches fail in a closed state. Amplifiers may optionally be disposed in each of the output signal lines.

US Patent:

59347740, Aug 10, 1999

Filed:

Feb 26, 1998

Appl. No.:

9/031110

Inventors:

Thomas Gordon Wu - Monterey Park CA
Robert Dennis Brunner - Los Gatos CA
Tina Zimmerman - San Francisco CA
Sung Hoon Kim - Palo Alto CA

Assignee:

Toshiba America Information System, Inc. - Irvine CA

International Classification:

F16M 1100

US Classification:

3122232

Abstract:

A chassis cover of a host unit, which has a horizontal orientation and a vertical orientation, includes a side cover and a stabilizing stand. The side cover has outer peripheral edges and a cavity. The stand is movable between a closed position and an open position and is coupled to the side cover. The stand fits within the cavity in the side cover to form a substantially contiguous surface when the host unit is in the horizontal orientation and the stand is in the closed position. The stand projects beyond the outer peripheral edges of the side cover in a direction transverse to the depth of the host unit to stabilize the host unit in the vertical orientation resting on the side cover when the stand is in the open position.

US Patent:

D4151208, Oct 12, 1999

Filed:

Mar 13, 1998

Appl. No.:

D/084980

Inventors:

John Joseph Daly - Irvine CA
Robert Dennis Brunner - Los Gatos CA
Barbara Sauceda - Palo Alto CA

Assignee:

Toshiba America Information Systems, Inc. - Irvine CA

International Classification:

1402

US Classification:

D14100

US Patent:

D4490452, Oct 9, 2001

Filed:

Oct 14, 1998

Appl. No.:

D/094981

Inventors:

John Daly - Irvine CA
Robert Brunner - Los Gatos CA
Barbara Sauceda - Palo Alto CA

Assignee:

Toshiba America Information Systems, Inc. - Irvine CA

International Classification:

1402

US Classification:

D14349

US Patent:

61097101, Aug 29, 2000

Filed:

Feb 26, 1998

Appl. No.:

9/031403

Inventors:

Thomas Gordon Wu - Monterey Park CA
Gary Phillip Elsasser - Mission Viejo CA
Robert Dennis Brunner - Los Gatos CA

Assignee:

Toshiba America Information Systems, Inc. - Irvine CA

International Classification:

H05K 718

US Classification:

3122232

Abstract:

A chassis cover for a host unit of a computer system is disclosed. The chassis cover is preferably capable of covering a chassis which includes mountings for components which are movable in a direction. The chassis cover includes a first surface, and a movable side door having a closed position and an open position. The side door provides an opening in the chassis cover when in the open position to permit the mountings to be extended toward the opening when the side door is in the open position. By permitting the mountings to be extended toward an opening provided by the side door, the components within the host unit may be accessed and serviced without removing a heavy display monitor.

US Patent:

59240318, Jul 13, 1999

Filed:

Jan 21, 1997

Appl. No.:

8/781370

Inventors:

Wilbert B. Copeland - Los Angeles CA
William L. Ballhaus - Venice CA
Robert A. Brunner - Redondo Beach CA
Arnold L. Berman - Los Angeles CA
Samuel A. Milliken - Playa del Rey CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H04B 7185

US Classification:

455428

Abstract:

Transponder systems are disclosed for routing signals from a plurality of input frequency channels at each of a plurality of receive antennas to a plurality of output frequency channels at each of a plurality of transmit antennas. The routing is preferably processed at an intermediate frequency. A plurality of bandpass filters are coupled to each receive antenna to define input signal paths. First and second mixers are positioned in series with each bandpass filter. A mixing signal at the first mixer adjusts the frequency of a selected one of the input signals to pass it through the bandpass filter and onto the respective input signal path. A mixing signal on the second mixer translates the frequency of that input signal to have a frequency order in the intermediate frequency band that corresponds with the frequency order of a selected one of the output frequency channels at its respective transmit antenna. Each of the transmit antennas is coupled to a common signal path of an adder. The adder has a plurality of intermediate signal paths which are each connected through a plurality of switches to a selected one of the input signal paths.