Robert P Busch

US Patent:

6430073, Aug 6, 2002

Filed:

Dec 6, 2000

Appl. No.:

09/730673

Inventors:

Kevin A. Batson - Williston VT
Robert E. Busch - Essex Junction VT
Garrett S. Koch - Jeffersonville VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49, 365149

Abstract:

A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a âhiddenâ refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.

US Patent:

6442055, Aug 27, 2002

Filed:

Dec 12, 2001

Appl. No.:

10/016025

Inventors:

Robert E. Busch - Essex Junction VT
Kevin A. Batson - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49, 36518907

Abstract:

A system and method is disclosed for operating a content addressable memory (CAM) within an integrated circuit using search signals at search input voltages which are substantially independent from an operating voltage of the CAM. A method is disclosed in which search signals are input to CAM cells of the CAM at search input voltages which are substantially independent of an operating voltage of storage elements within the CAM cells. A match signal is output upon detecting a matching condition between the search signals and data stored in the storage elements. The search input voltage can be within about 0. 2V above a threshold voltage of a search input device of the CAM memory cell. Search input devices can be selected to have a lower threshold voltage than other devices included within the CAM cell.

US Patent:

6487101, Nov 26, 2002

Filed:

Oct 2, 2001

Appl. No.:

09/968814

Inventors:

Jonathan B. Ashbrook - Huntington VT
Robert E. Busch - Essex Junction VT
Albert M. Chu - Essex Junction VT
Daryl M. Seitzer - Richmond VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49

Abstract:

A method and structure for a content addressable memory (CAM) array having a plurality of memory cells. Each of the memory cells has capacitive storage devices, transistors connected to the storage devices, a wordline connected to and controlling the transistors, bitlines connected to the storage devices through the transistors, combined search and global bitlines connected to the capacitive storage devices. These cells are further arranged into columns, each containing multiplexers connected to the combined search and global bitlines, data-in lines connected to the multiplexers, and search-data lines connected to the multiplexers. Further, the multiplexers select between the data-in lines and the search-data lines to allow the combined search and global bitlines to be alternatively used as data lines and search lines. Also, in the invention each of the columns further has drivers between the multiplexers and the combined search and global bitlines. The drivers drive signals between the multiplexers and the combined search and global bitlines during search and write operations.

US Patent:

6501675, Dec 31, 2002

Filed:

May 14, 2001

Appl. No.:

09/854987

Inventors:

Harold Pilo - Underhill VT
Robert E. Busch - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1124

US Classification:

365149, 365190

Abstract:

A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycles reference bitline generation.

US Patent:

6650561, Nov 18, 2003

Filed:

Jan 30, 2002

Appl. No.:

10/059863

Inventors:

Kevin A. Batson - Williston VT
Geordie M. Braceras - Essex Junction VT
Robert E. Busch - Essex Junction VT
Gary S. Koch - Jeffersonville VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49

Abstract:

A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

US Patent:

6687144, Feb 3, 2004

Filed:

May 6, 2003

Appl. No.:

10/430671

Inventors:

Kevin A. Batson - Williston VT
Geordie M Braceras - Essex Junction VT
Robert E. Busch - Essex Junction VT
Gary S. Koch - Jeffersonville VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49, 365154

Abstract:

A high-reliability content addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

US Patent:

6728123, Apr 27, 2004

Filed:

Apr 15, 2002

Appl. No.:

10/123493

Inventors:

Kevin A. Batson - Williston VT
Robert E. Busch - Essex Junction VT
Gary S. Koch - Jeffersonville CT
Fred J. Towler - Essex Junction VT
Reid A. Wistort - Westford VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1502

US Classification:

365 49, 365200

Abstract:

The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.

US Patent:

6760240, Jul 6, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/065822

Inventors:

Robert E. Busch - Essex Junction VT
Albert M. Chu - Essex Junction VT
Ezra D. B. Hall - Richmond VT
Paul C. Parries - Wapingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49, 36518907, 365 63

Abstract:

A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macros are inverted with respect to adjacent macros to balance parasitic capacitances across the array.