Robert Louis Caulk

US Patent:

7139291, Nov 21, 2006

Filed:

Apr 4, 2002

Appl. No.:

10/116664

Inventors:

Ygal Arbel - Belmont CA, US
Robert Louis Caulk - Livermore CA, US

Assignee:

Bay Microsystems, Inc. - San Jose CA

International Classification:

H04J 3/02
H04L 12/28
H04L 12/56
H04L 12/66

US Classification:

370537, 370422, 370539

Abstract:

A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

US Patent:

7184662, Feb 27, 2007

Filed:

Oct 10, 2001

Appl. No.:

09/974448

Inventors:

Ygal Arbel - Belmont CA, US
Robert Louis Caulk - Livermore CA, US

Assignee:

Bay Microsysems, Inc. - San Jose CA

International Classification:

H04J 14/00

US Classification:

398 56, 398 45, 370372

Abstract:

A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.

US Patent:

7707363, Apr 27, 2010

Filed:

May 23, 2006

Appl. No.:

11/419889

Inventors:

Robert Louis Caulk - Livermore CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711149, 711 5, 711E12003

Abstract:

An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

US Patent:

7752398, Jul 6, 2010

Filed:

May 23, 2006

Appl. No.:

11/419888

Inventors:

Robert Louis Caulk - Livermore CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711149, 711 5, 711E12003, 36523005

Abstract:

An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

US Patent:

20070274398, Nov 29, 2007

Filed:

May 23, 2006

Appl. No.:

11/419882

Inventors:

Robert Louis Caulk - Livermore CA, US

Assignee:

METTA TECHNOLOGY, INC. - San Jose CA

International Classification:

H04N 7/12

US Classification:

37524026

Abstract:

A method of parallelizing the prediction of H.264 luma blocks is disclosed. The illustrative embodiment, for example, enables the prediction of H.264 luma blocks to be performed in parallel on a single-instruction, multiple-data processor so that any two—and up to all 16 pixels—can be set simultaneously in different execution units. This is very fast and economical. The invention of formulas for enabling the parallelization of the H.264 luma blocks is noteworthy because of the diversity in the structures of the formulas for predicting the various pixels given by the H.264 standard. For example, the standard specifies fundamentally different formulas for some pixels than for others, which makes their parallelization appear impossible.

US Patent:

57375623, Apr 7, 1998

Filed:

Oct 6, 1995

Appl. No.:

8/540382

Inventors:

Robert L. Caulk - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 930

US Classification:

395394

Abstract:

A pipelined microprocessor is provided with a queuing stage between an instruction fetch stage and an instruction decode stage to facilitate branch instructions and to receive instructions from the fetch stage when the decode stage is stalled. If a branch is incorrectly anticipated the queuing stage has nonbranch sequential instructions for the decode stage while the fetch stage is restarted at the nonbranch sequential instruction stream.

US Patent:

57649391, Jun 9, 1998

Filed:

Oct 6, 1995

Appl. No.:

8/540350

Inventors:

Robert L. Caulk - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 9305

US Classification:

395381

Abstract:

An add with circular mask operation is executed in a RISC processor which includes a coprocessor having a register for storing a circular mask value. A circular mask instruction to the coprocessor includes a value in an immediate field and identifies a general register (RS), and a destination register (RT). The coprocessor operates on the value stored in the general register with the value in the immediate field and then masks the results using the circular mask value. The results are then stored in the destination register. The operation includes sign-extending the immediate field before adding to the contents of the general register to provide a sum, and the sum is then masked with the circular mask value.

US Patent:

56030479, Feb 11, 1997

Filed:

Oct 6, 1995

Appl. No.:

8/540336

Inventors:

Robert L. Caulk - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 900

US Classification:

395800

Abstract:

A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing. One of the registers is a circulate mask register which is used by the coprocessor in executing an Add with Circular Mask instruction in which an immediate field of the instruction is sign-extended and added to the contents of a general register, the result being masked with the extended value in the circular mask register.