Robert A Curtis

US Patent:

59635991, Oct 5, 1999

Filed:

Aug 4, 1997

Appl. No.:

8/905577

Inventors:

Robert G. Curtis - Sudbury MA
Wesley G. Brodsky - Medford MA

Assignee:

Raytheon Company - Lexington MA

International Classification:

H03D 100
H04L 2706
H04L 2302
H04L 512

US Classification:

375341

Abstract:

A truncated maximum likelihood sequence estimator that provides a best estimate of a transmitted symbol sequence includes a lookup table and a comparator. The lookup table may be responsive to at least a next sample of a received RF signal, a first decision made on a first previous sample of the RF received signal and a second decision made on the second previous sample of the RF received signal. The lookup table provides at an output at least one threshold value stored in the lookup table that is addressed by the next sample of the received signal, the first decision made on the first previous sample and the second decision made on the second previous sample. The comparator is coupled to the output of a lookup table and is responsive to the at least one threshold value and a current sample of the received RF signal. The comparator compares the current sample of the received RF signal with at least one threshold value and provides a best estimate of the transmitted symbol sequence. The truncated maximum likelihood sequence estimator can be used for example to determine a best estimate of a transmitted symbol sequence of a current sample of 4-ary frequency shift keyed signal or a 2-ary frequency shift keyed received signal.

US Patent:

49741900, Nov 27, 1990

Filed:

Dec 5, 1988

Appl. No.:

7/280149

Inventors:

Robert A. Curtis - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H04Q 900

US Classification:

364900

Abstract:

A pass-through and isolation switch for connecting a terminal to a computer and for disconnecting the terminal from the computer without disrupting any sessions which may have been opened on the computer by the terminal. The switch includes a first gate and a second gate for switching in and out balanced termination loads across corresponding input terminals of the switch depending on the state of a control signal. And it includes a third gate and a fourth gate for preventing or allowing the passage of signals between the terminal and the computer, also depending upon the state of the control signal.

US Patent:

47698160, Sep 6, 1988

Filed:

Nov 8, 1985

Appl. No.:

6/796344

Inventors:

Gary H. Hochstadt - Framingham MA
Robert G. Curtis - Sudbury MA
Richard G. Berard - Chelmsford MA

Assignee:

Raytheon Company - Lexington MA

International Classification:

H04J 306

US Classification:

370100

Abstract:

A receiver including two optimizers for demodulation, sampling and quantization of received QPSK digital data. One optimizer adjusts the phase of a reference signal used for demodulating the QPSK data into baseband in-phase and quadrature channels and another optimizer adjusts a sampling clock used to sample and quantize the baseband channels. The reference signal and the sampling clock are dithered in quadrature. Variations in the amplitude of the quantized data extracted by an eye quality monitor. Each optimizer multiplies the eye quality monitor output by a corresponding dither clock and integrates to form an error signal. Phase shifters, responsive to corresponding error signals and dithered clocks, adjust the phase of the demodulation reference signal and sampling clock. The data quality signal monitor translates the magnitude of the quantized data signals to a common set of signals for each state of the data signal. These common signals are translated into a voltage representing the degree to which the data signal amplitude corresponds to a predetermined value.

US Patent:

48752231, Oct 17, 1989

Filed:

Sep 8, 1987

Appl. No.:

7/093974

Inventors:

Robert A. Curtis - Marlboro MA

Assignee:

Digital Equipment Corporation - Manyard MA

International Classification:

H04B 300
H04L 2500

US Classification:

375 36

Abstract:

An adapter for allowing high frequency local area network signals to be transmitted over low cost twisted pair cable. The adapter performs two functions, to act as a converter to match the impedance of the coaxial cable to that of twisted pair cable, as well as an output balancer, to insure that the alternating current or high frequency components of the signals sent over the twisted pair cable are complementary. Only one of the complementary signals carries DC collision information.

US Patent:

52238067, Jun 29, 1993

Filed:

Aug 23, 1991

Appl. No.:

7/748947

Inventors:

Robert A. Curtis - Hudson MA
Dusan S. Skendzic - Boston MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H04B 328

US Classification:

333 12

Abstract:

A computer network interface ("NIC") exhibits reduced electromagnetic interference and emission through capacitively coupling an output transformer center tap both to reference ground and to logic ground of the NIC's transceiver. Transmit signal lines on both sides of the transceiver are also capacitively coupled to both grounds. Other aspects of the invention reduce electromagnetic interference and emission through improvements in the construction of the NIC printed circuit board and the technique for intercoupling a plurality of NIC's using shielded twisted-pair cable.

US Patent:

44492235, May 15, 1984

Filed:

Apr 30, 1982

Appl. No.:

6/373763

Inventors:

Nathan A. Liskov - Waltham MA
Robert G. Curtis - Sudbury MA
Caesar J. Favaloro - Sudbury MA
Gregory L. Pence - Allen Park MI

Assignee:

Raytheon Company - Lexington MA

International Classification:

H03K 1332

US Classification:

375 10

Abstract:

An eye opening monitor for a binary waveform such as provided as the video output of a demodulator. At the decision sample time, the video is compared to -V. sub. th and +V. sub. th reference voltages to determine if it falls in the range defined therebetween. If it does, a counter is reset. Because the carry-out pulses of the counter are used to produce -V. sub. th and +V. sub. th, the range defined therebetween is decreased by the additional time required to count to the carry-out after the counter is reset. The loop stabilizes with the range from -V. sub. th and +V. sub. th being quantitatively indicative of the eye opening. A voltage derived from V. sub. th is visually displayed.

US Patent:

52552870, Oct 19, 1993

Filed:

Jun 28, 1991

Appl. No.:

7/723085

Inventors:

David C. Davies - Chelmsford MA
Donald G. Vonada - Stow MA
Robert A. Curtis - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H04L 2534

US Classification:

375 17

Abstract:

Transceiver apparatus includes a transmitter circuit constructed with either emitter coupled logic (ECL) circuitry or programmable array logic circuitry, and a receiver circuit constructed with ECL circuitry. The transmitter circuit encodes a binary data signal received for transmission as a three-level modified duobinary encoded data signal and the receiver circuit decodes the received three-level encoded data signal to provide a binary data signal corresponding to the data signal received at the transmitter circuit for transmission. Both the transmitter and receiver circuits include features enabling transmitting and receiving high data-rate data signals.

US Patent:

53393074, Aug 16, 1994

Filed:

Apr 23, 1993

Appl. No.:

8/052808

Inventors:

Robert A. Curtis - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H04J 302
H04L 2540

US Classification:

370 131

Abstract:

A data communication system having a plurality of nodes is disclosed. A number of transceivers is provided, each transceiver being coupled to a respective one of the plurality of nodes, for data communication between the transceiver and its associated node. Each transceiver is also provided with a controlled current source. The data communication system is also equipped with a data bus for communication of a transmitted data signal between the transceivers. A current bus which is coupled to each transceiver receives a current signal from the controlled current source when a transceiver is placing the data onto the data bus.