Robert P Davidson

US Patent:

6724079, Apr 20, 2004

Filed:

Jan 4, 2002

Appl. No.:

10/039800

Inventors:

Lakshminarayan Viswanathan - Phoenix AZ
Pierre-Marie Piel - Tempe AZ
Garry D. Funk - Scottsdale AZ
Robert Paul Davidson - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2312

US Classification:

257704, 257341, 257343, 257401, 257666, 257668, 257789, 257791, 361792

Abstract:

A wire bond-less electronic component is for use with a circuit external to the wire bond-less electronic component. The wire bond-less electronic component includes a support substrate ( ), an electronic device ( ) over the support substrate, and a cover ( ) located over the electronic device and the support substrate. The cover includes an interconnect structure ( ) electrically coupled to the electronic device and adapted to electrically couple together the electronic device and the circuit for providing impedance transformation of an electrical signal between the electronic device and the circuit.

US Patent:

6844221, Jan 18, 2005

Filed:

Apr 9, 2004

Appl. No.:

10/821749

Inventors:

Lakshminarayan Viswanathan - Phoenix AZ, US
Pierre-Marie Piel - Tempe AZ, US
Garry D. Funk - Scottsdale AZ, US
Robert Paul Davidson - Chandler AZ, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438125, 257718, 257719, 257727, 257728

Abstract:

A wire bond-less electronic component is for use with a circuit external to the wire bond-less electronic component. The wire bond-less electronic component includes a support substrate (), an electronic device () over the support substrate, and a cover () located over the electronic device and the support substrate. The cover includes an interconnect structure () electrically coupled to the electronic device and adapted to electrically couple together the electronic device and the circuit for providing impedance transformation of an electrical signal between the electronic device and the circuit.

US Patent:

20130105892, May 2, 2013

Filed:

Oct 31, 2011

Appl. No.:

13/285557

Inventors:

XIAOWEI REN - Phoenix AZ, US
Robert P. Davidson - Chandler AZ, US
Mark A. Detar - Round Rock TX, US

International Classification:

H01L 21/336
H01L 29/78

US Classification:

257335, 438286, 438289, 257E29256, 257E21417

Abstract:

A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.

US Patent:

55282024, Jun 18, 1996

Filed:

Dec 23, 1994

Appl. No.:

8/363200

Inventors:

Daniel D. Moline - Chandler AZ
Robert P. Davidson - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03H 738

US Classification:

333 33

Abstract:

A technique for achieving impedance transformations utilizing transmission lines has been provided. This technique involves placing additional distributed capacitance along the length of a transmission line thereby reducing the effective characteristic impedance of the transmission line. The effective wavelength for the transmission line is also reduced thereby substantially reducing the electrical length of a quarter wavelength matching network and making the transmission line practical and effective even at low frequencies.

US Patent:

49856863, Jan 15, 1991

Filed:

Dec 4, 1989

Appl. No.:

7/446228

Inventors:

Robert P. Davidson - Chandler AZ
Richard A. Rose - Hoffman Estates IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 368

US Classification:

330124R

Abstract:

An active load impedance control system for a radio frequency power amplifier comprising an amplification means for amplifying radio frequency signals and providing a forward signal, a control means responsive to the operating conditions of said amplification means, a correction signal means responsive to the control means for providing an amplitude, a sampling means and phase controlled corrective reflective signal and a combining means for combining said forward signal and said corrective reflective signal.

US Patent:

20140284716, Sep 25, 2014

Filed:

Jun 11, 2014

Appl. No.:

14/302174

Inventors:

Xiaowei Ren - Phoenix AZ, US
David C. Burdeaux - Tempe AZ, US
Robert P. Davidson - Chandler AZ, US
Michele L. Miera - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/78
H01L 29/66

US Classification:

257343, 438303

Abstract:

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.

US Patent:

20140252467, Sep 11, 2014

Filed:

May 26, 2014

Appl. No.:

14/287143

Inventors:

- AUSTIN TX, US
ROBERT P. DAVIDSON - CHANDLER AZ, US
MARK A. DETAR - ROUND ROCK TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - AUSTIN TX

International Classification:

H01L 29/78
H01L 29/10

US Classification:

257336

Abstract:

Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.

US Patent:

20140117446, May 1, 2014

Filed:

Oct 31, 2012

Appl. No.:

13/665665

Inventors:

Xiaowei Ren - Phoenix AZ, US
David C. Burdeaux - Tempe AZ, US
Robert P. Davidson - Chandler AZ, US
Michele L. Miera - Gilbert AZ, US

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257343, 438302, 257E29256, 257E21417

Abstract:

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.