Robert C Demoss

US Patent:

51366525, Aug 4, 1992

Filed:

Nov 14, 1985

Appl. No.:

6/798057

Inventors:

Mahmoud K. Jibbe - Wichita KS
Robert A. DeMoss - Wichita KS
Elmer A. Hoyer - Wichita KS
Merle E. Furry - Wichita KS

Assignee:

NCR Corporation - Dayton OH

International Classification:

H04N 712
H04B 700

US Classification:

381 31

Abstract:

An encoder and a decoder is provided with each being usable independently of each other for improving the dynamic range of clipped speech digital systems by providing amplitude components to the clipped digital signal. The encoder processes an audio input signal along two signal paths, the first signal path including a clipper and digitizer means for forming a digitized clipped signal. The second signal path includes a rectifier, envelope detector and digitizing means for forming a digitized signal having amplitude components. Both digitized signals may then be transmitted to the decoder for reconstruction or stored for reconstruction at a later time.

US Patent:

57784116, Jul 7, 1998

Filed:

Sep 18, 1997

Appl. No.:

8/933327

Inventors:

Robert A. DeMoss - Wichita KS
Donald R. Humlicek - Wichita KS

Assignee:

Symbios, Inc. - Fort Collins CO

International Classification:

G06F 1210

US Classification:

711 4

Abstract:

A method and corresponding controller apparatus for creating, updating and maintaining mapping information in a virtual mass storage subsystem. A request to manipulate a virtual block or cluster identifies a particular virtual block number. The virtual block number is mapped to a first physical block number by a direct calculation. A header data structure contained in the first physical block contains mapping information to locate other physical blocks associated with the virtual cluster. In addition to the header data structure, the first physical block contains a portion of the stored data for the corresponding virtual cluster. Additional physical blocks which stored the data of the virtual cluster are located from the mapping information in the header of the first physical block. The methods of the present invention provide improved performance and reduced buffer memory requirements in the virtual mass storage controller circuits of the subsystem as compared to prior approaches.

US Patent:

54189250, May 23, 1995

Filed:

Oct 23, 1992

Appl. No.:

7/966107

Inventors:

Robert A. DeMoss - Wichita KS
Keith B. DuLac - Derby KS

Assignee:

AT&T Global Information Solutions Company - Dayton OH

International Classification:

G06F 1300

US Classification:

395425

Abstract:

A method for reducing the apparent response time for write I/O operations initiated by a host system to a RAID level 3, 4 or 5 disk array including a spare disk drive. The disclosed method comprises the steps of (1) saving write data received by the disk array from the host system directly to the spare drive, (2) issuing a write complete status signal to the host system indicating completion of the host write I/O operation, thus freeing the host processor to perform other functions, and (3) transferring the data saved to the spare drive to the active drives within the array. This third step may be executed at any convenient time following the second step. For example, in systems where a host processor functions as the array controller, this third step may be delayed while higher priority tasks are executed. In systems where the disk array includes an array controller, the array controller coordinates the execution of this third step with other controller or array operations to optimize array operation. In additiona, the data from multiple write I/O opertions may be accumulated to the spare drive prior to the step of transferring the data saved to the spare drive to the other, active, drives within the array.

US Patent:

60165278, Jan 18, 2000

Filed:

Sep 30, 1996

Appl. No.:

8/724596

Inventors:

Robert A. DeMoss - Wichita KS

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1314

US Classification:

710117

Abstract:

Methods and associated apparatus for improving the fairness of bus allocation in association with standard SCSI bus arbitration. The present invention provide a plurality of time slots each of which define a delay period following the SCSI specified minimum period before arbitration is allowed to begin. Each device which requires arbitration on the SCSI bus pseudo-randomly selects one of the time slots before attempting SCSI bus arbitration. The device then delays the associated period of time before commencing SCSI bus arbitration. At any time before the end of the delay period, if the device senses that the SCSI bus has again become busy, then the device has already lost the arbitration without actually competing therefore. A second device, having selected a time slot with a shorter delay period, has won control of the SCSI bus before the first device attempted arbitration. The time slots are selected with a probability associated with each slot.

US Patent:

6138125, Oct 24, 2000

Filed:

Mar 31, 1998

Appl. No.:

9/052894

Inventors:

Robert A. DeMoss - Wichita KS

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1730

US Classification:

707202

Abstract:

A method, system, and data structure for encoding a block of data with redundancy information and for correction of erasure type errors in the block using the redundancy data. In particular, the invention is particularly applicable to disk array storage subsystems which are capable of recovering from total or partial failures of one or two disks in the disk array. Still more specifically, the invention is applicable to RAID level 6 storage devices. A given data block of data is translated into a code block of n. sup. 2 elements including 2n XOR parity elements for redundancy. Each code block is manipulated as a square matrix, of n. sup. 2 elements with parity elements along the major diagonals of the matrix and data elements in the remainder of the matrix. Each parity element is a dependent variable whose value is the XOR sum of the (n-2) data elements in a minor diagonal which intersects it. If the elements in any one or two columns or one or two rows are erased, their values can be generated from the other elements in the matrix.

US Patent:

53881087, Feb 7, 1995

Filed:

Oct 23, 1992

Appl. No.:

7/966106

Inventors:

Robert A. DeMoss - Wichita KS
Keith B. DuLac - Derby KS

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1100

US Classification:

371 511

Abstract:

An improved method for updating data and parity information in a RAID level 4 or 5 disk array employing a read-modify-write (RMW) process for updating data and parity information. During normal RMW operations, the old data and old parity information to be updated are read from disk, new parity is generated, and the new parity information and new data written to disk. The improved RMW method separates the execution of data read and write operations from the execution of parity read, generation and write operations to permit greater efficiency in the utilization of the drives within the array. The method identifies the disk drives containing the data and parity to be updated and places the proper read and write requests into the I/O queues for the identified data and parity drives, scheduling parity operations; i. e. reading old parity information from the parity drive, generating new parity information and writing the new parity information to the parity drive; for execution when best accommodated in the I/O queue for the parity drive, following the read of old data from the data drive.