Robert D Dixon

US Patent:

6496911, Dec 17, 2002

Filed:

Oct 2, 1998

Appl. No.:

09/165954

Inventors:

Robert Christopher Dixon - Austin TX
Thoi Nguyen - Austin TX
Tuan Hoang Nguyen - Burien WA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711170, 709105

Abstract:

An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.

US Patent:

6581190, Jun 17, 2003

Filed:

Nov 30, 1999

Appl. No.:

09/451955

Inventors:

Robert Christopher Dixon - Austin TX
Timothy Michael Lambert - Austin TX
Howard Carl Tanner - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 4, 716 6, 714724, 714728, 714726, 714727, 714 30

Abstract:

A method in a data processing system for identifying a circuit. In a preferred embodiment, a set of bits, with a defined chain length, are shifted into the circuit one bit at a time. The bits shifted out from the circuit are compared to the bits, from the set of bits, shifted into the circuit to determine if the circuit corresponds to a first type circuit. The comparing step is accomplished before all bits in the set of bits have been shifted into the circuit. If the circuit is not a first type circuit corresponding to the set of bits shifted into the circuit, then the shifting of bits into the circuit is discontinued and the process is repeated with a second set of bits corresponding to a second circuit type until the circuit type has been identified.

US Patent:

6657325, Dec 2, 2003

Filed:

Jan 11, 2001

Appl. No.:

09/758863

Inventors:

Robert Christopher Dixon - Austin TX
Thoi Nguyen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02J 700

US Classification:

307149, 307413

Abstract:

A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e. g. , a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan.

US Patent:

6757617, Jun 29, 2004

Filed:

Jan 23, 2001

Appl. No.:

09/768074

Inventors:

Robert Christopher Dixon - Austin TX
Chad J. Larson - Ames IA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05D 2300

US Classification:

702 25, 702 34, 702 41, 702 64, 702 65, 702 66, 702 69, 702 70

Abstract:

A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation, including a number of waveform shaping networks coupled to a corresponding one of the fans and utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. The frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal, and a frequency discriminator, coupled to the summing circuit, that separates the single combined signal into multiple components, wherein each of the multiple components corresponds to a particular fan.

US Patent:

6820226, Nov 16, 2004

Filed:

Jan 7, 2002

Appl. No.:

10/042097

Inventors:

Robert Christopher Dixon - Austin TX
Alan Grant Singletary - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724, 714 25, 3241581

Abstract:

In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.

US Patent:

6865641, Mar 8, 2005

Filed:

Aug 29, 2002

Appl. No.:

10/232253

Inventors:

Robert Christopher Dixon - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711103, 359242, 359277, 359293, 345 84

Abstract:

In one form of the invention, an apparatus for visually displaying a non-volatile message includes an integrated circuit having first circuitry. The apparatus also includes a package for the integrated circuit and a display affixed to the integrated circuit package. The first circuitry is coupled to the display and operable to be coupled to an electronic device by pins of the integrated circuit package and to write a non-volatile, visual image via the display responsive to receiving a message from the electronic device.

US Patent:

6981166, Dec 27, 2005

Filed:

Jan 7, 2002

Appl. No.:

10/042104

Inventors:

Robert Christopher Dixon - Austin TX, US
Alan Grant Singletary - Austin TX, US
Barry Joe Wolford - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F001/04

US Classification:

713500, 713400

Abstract:

In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the clock, respectively. X cycles of the clock correspond to a time interval T with the clock operating at the frequency f, and, accordingly, the device is capable of performing X/Y instances of the second operation within time interval T with the clock operating at the frequency f. During the time interval T at least one extra cycle of the clock is generated to reduce performance time for the first operation. An affect of the at least one extra cycle is masked with respect to the second operation, so that instances of the second operation during the interval T remain no greater in number than X/Y.

US Patent:

7129769, Oct 31, 2006

Filed:

Feb 17, 2005

Appl. No.:

11/060355

Inventors:

Robert Christopher Dixon - Austin TX, US
William Paul Hovis - Rochester MN, US
Kirk Edward Morrow - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01H 37/76

US Classification:

327525, 3652257

Abstract:

A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is being blown, the constant current is diverted away from the core to the eFuse and as the eFuse blows, the constant current is again dumped to the semiconductor core. Thus, a change in current due to the transient of the eFuse being blown is not detectable and the information that an eFuse has been blown is kept secure.