Robert L English

US Patent:

6353844, Mar 5, 2002

Filed:

Dec 23, 1996

Appl. No.:

08/773486

Inventors:

Nawaf K. Bitar - San Jose CA
Robert M. English - Menlo Park CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 950

US Classification:

709102

Abstract:

A batch job scheduler facility schedules batch jobs in a general purpose multiprocessor system having resources, such as processors and memory, and running interactive and batch jobs. The resources are allocated to the batch jobs. Completion times are calculated and guaranteed for the batch jobs based on the resources allocated to the batch jobs. The completion times are calculated and guaranteed without static partitioning, resulting in improved utilization of system resources. Batch-critical batch jobs are defined which require all their allocated resources to complete by their guaranteed completion time. The batch jobs are scheduled so that batch jobs and interactive jobs compete for the same resources. Batch-critical jobs are permitted to obtain all their allocated resources.

US Patent:

6418460, Jul 9, 2002

Filed:

Feb 18, 1997

Appl. No.:

08/802802

Inventors:

Nawaf K. Bitar - San Jose CA
Robert M. English - Menlo Park CA
Rajagopal Ananthanarayanan - Sunnyvale CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 900

US Classification:

709108, 712233

Abstract:

A system and method for inexpensively detecting preempted execution entities such as threads without kernel involvement. In a computer system having a memory and one or more processors, a shared memory arena is formed in user space within the memory. A preempt bit vector is then formed within the shared memory arena such that the preempt bit vector is accessible to any of a plurality of execution entities running in user mode. The preempt bit vector includes a plurality of rbits, wherein each rbit is associated with one of the plurality of execution entities and wherein an rbit is marked whenever its associated execution entity is preempted. Detection of preempted threads then becomes a matter of reading, via program code executing in user mode on one of the plurality of processors, bits in the preempt bit vector to detect preempted execution entities.

US Patent:

6714960, Mar 30, 2004

Filed:

Nov 20, 1996

Appl. No.:

08/752909

Inventors:

Nawaf K. Bitar - San Jose CA
Robert M. English - Menlo Park CA
Rajagopal Ananthanarayanan - Sunnyvale CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 900

US Classification:

709103

Abstract:

A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to each job.

US Patent:

6766515, Jul 20, 2004

Filed:

Feb 18, 1997

Appl. No.:

08/801646

Inventors:

Nawaf K. Bitar - San Jose CA
Robert M. English - Menlo Park CA
Rajagopal Ananthanarayanan - Sunnyvale CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 900

US Classification:

718100, 718101, 718108, 712 41, 712228

Abstract:

A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the applications user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an applications register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an applications user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.

US Patent:

6874027, Mar 29, 2005

Filed:

Jun 9, 2000

Appl. No.:

09/590491

Inventors:

Robert M. English - Menlo Park CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F015/173

US Classification:

709226, 709201, 718102

Abstract:

A method and system for providing the functionality of dynamically-allocated threads in a multithreaded system, in which the operating system provides only statically-allocated threads. With this functionality, a relatively large number of threads can be maintained without a relatively large amount of overhead (either in memory or processor time), and it remains possible to produce program code without undue complexity. A plurality of dynamically-allocated threads are simulated using a single statically-allocated thread, but with state information regarding each dynamically-allocated thread maintained within the single statically-allocated thread. The single statically-allocated thread includes, for each procedure call that would otherwise introduce a new simulated thread, a memory block including (1) a relatively small procedure call stack for the new simulated thread, and (2) a relatively small collection of local variables and other state information for the new simulated thread.

US Patent:

7073115, Jul 4, 2006

Filed:

Dec 28, 2001

Appl. No.:

10/035603

Inventors:

Robert M. English - Menlo Park CA, US
Peter F. Corbett - Lexington MA, US
Steven R. Kleiman - Los Altos CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G11C 29/00
G06F 11/00

US Classification:

714770, 714 6, 711114

Abstract:

A technique efficiently corrects multiple storage device failures in a storage array using a combination of a single diagonal parity group and multiple row parity groups. The storage array includes a plurality of concatenated sub-arrays, wherein each sub-array includes a set of data storage devices and a parity storage device. Each row parity group is associated with a sub-array of the array. The array further includes a global parity storage device holding diagonal parity computed across the concatenation of the sub-arrays. Instead of requiring that each parity group contain both a row parity device and a diagonal parity device, the array is composed of a collection of row parity groups. Diagonal parity is calculated across the full array.

US Patent:

7080278, Jul 18, 2006

Filed:

Mar 8, 2002

Appl. No.:

10/094086

Inventors:

Steven R. Kleiman - Los Altos CA, US
Robert M. English - Menlo Park CA, US
Peter F. Corbett - Lexington MA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 11/00

US Classification:

714 6, 714755, 714800, 714804

Abstract:

A technique efficiently corrects multiple storage device failures in a storage array. The storage array comprises a plurality of concatenated sub-arrays, wherein each sub-array includes a set of data storage devices and a local parity storage device that stores values used to correct a failure of a single device within a row of blocks, e. g. , a row parity set, in the sub-array. Each sub-array is assigned diagonal parity sets identically, as if it were the only one present using a double failure protection encoding method. The array further includes a single, global parity storage device holding diagonal parity computed by logically adding together equivalent diagonal parity sets in each of the sub-arrays.

US Patent:

7139817, Nov 21, 2006

Filed:

Jun 12, 2001

Appl. No.:

09/879840

Inventors:

Robert M. English - Menlo Park CA, US
Brian Quirion - San Jose CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 15/177

US Classification:

709220, 709221, 709222, 710 8, 710 9, 710 10, 713 1, 713 2, 713100

Abstract:

The invention provides for managing information for multiple devices. Each of a set of devices retrieves information from a sequence of servers. A device when starting up reads a list of file names, reads information from each file in sequence, and resolves conflicts among files to present a consistent configuration on each restart of each device. A file includes a sequence of pairs. In those cases when two variables have the same name, an operator associated with the second pair indicates whether to overwrite the first value or to edit the first value, such as by appending the second value. One of the pairs indicates the list of file names itself. When the list of file names is changed, the device for which the change is made re-reads the sequence of files and repeats its determination of the pairs, until the list of file names is stabilized.