Robert W Erickson

US Patent:

6438735, Aug 20, 2002

Filed:

May 17, 1999

Appl. No.:

09/310882

Inventors:

Kenneth S. McElvain - Los Altos CA
Robert Erickson - Cupertino CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 7, 716 1

Abstract:

Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e. g. a particular IC vendors architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e. g. field programmable gate arrays). In an example of another method, an HDL code is compiled to produce an RTL netlist representation which specifies a plurality of ICs in which logic, designed for placement on one of the plurality of ICs, is replicated for placement on another one of the plurality of ICs.

US Patent:

6519754, Feb 11, 2003

Filed:

May 17, 1999

Appl. No.:

09/313225

Inventors:

Kenneth S. McElvain - Los Altos CA
Robert Erickson - Cupertino CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 18, 716 2, 716 5

Abstract:

Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

US Patent:

6668364, Dec 23, 2003

Filed:

Jun 3, 2002

Appl. No.:

10/162270

Inventors:

Kenneth S. McElvain - Los Altos CA
Robert Erickson - Cupertino CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 7, 716 5

Abstract:

Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTh netlist is mapped to a particular target technology (e. g. a particular IC vendors architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e. g. field programmable gate arrays). Other examples of methods and apparatuses are described.

US Patent:

6978430, Dec 20, 2005

Filed:

Dec 8, 2003

Appl. No.:

10/731312

Inventors:

Kenneth S. McElvain - Los Altos CA, US
Robert Erickson - Cupertino CA, US

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F009/45
G06F017/50

US Classification:

716 7, 716 11, 716 18

Abstract:

Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e. g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e. g. field programmable gate arrays). In an example of another method, an HDL code is compiled to produce an RTL netlist representation which specifies a plurality of ICs in which logic, designed for placement on one of the plurality of ICs, is replicated for placement on another one of the plurality of ICs.

US Patent:

7010769, Mar 7, 2006

Filed:

Dec 5, 2002

Appl. No.:

10/313523

Inventors:

Kenneth S. McElvain - Los Altos CA, US
Robert Erickson - Cupertino CA, US

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 9, 716 10, 716 16, 716 18, 716 7

Abstract:

Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

US Patent:

7275233, Sep 25, 2007

Filed:

Mar 4, 2003

Appl. No.:

10/382342

Inventors:

Kenneth S. McElvain - Los Altos CA, US
Robert Erickson - Cupertino CA, US

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

US Patent:

7454732, Nov 18, 2008

Filed:

Oct 18, 2005

Appl. No.:

11/254196

Inventors:

Kenneth S. McElvain - Los Altos CA, US
Robert Erickson - Cupertino CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 7, 716 2, 716 18

Abstract:

Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology independent register transfer level (RTL) netlist, which is to be partitioned between multiple ICs. Based on the estimation, the RTL netlist is partitioned between the multiple ICs. In response to the partition and the estimation, immediate feedback information is provided to a user.

US Patent:

7631282, Dec 8, 2009

Filed:

Aug 21, 2007

Appl. No.:

11/842911

Inventors:

Kenneth S. McElvain - Los Altos CA, US
Robert Erickson - Cupertino CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 6

Abstract:

Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.