Robert M Farrell

US Patent:

8275384, Sep 25, 2012

Filed:

Mar 20, 2010

Appl. No.:

12/728205

Inventors:

Rajarshi Das - New Rochelle NY, US
Robert George Farrell - Cornwall NY, US
Nitendra Rajput - New Delhi, IN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04W 72/00

US Classification:

4554521, 455450

Abstract:

Techniques for organizing information in a user-interactive system based on user interest are provided. In one aspect, a method for operating a system having a plurality of resources through which a user can navigate is provided. The method includes the following steps. When the user accesses the system, the resources are presented to the user in a particular order. Interests of the user in the resources presented are determined. The interests of the user are compared to interests of other users to find one or more subsets of users to which the user belongs by virtue of having similar interests. Upon one or more subsequent accesses to the system by the user, the order in which the resources are presented to the user is based on interests common to the one or more subsets of users to which the user belongs.

US Patent:

46370242, Jan 13, 1987

Filed:

Nov 2, 1984

Appl. No.:

6/667520

Inventors:

Jerry D. Dixon - Boca Raton FL
Robert H. Farrell - Coral Springs FL
Gerald A. Marazas - Boca Raton FL
Andrew B. McNeill - Deerfield Beach FL
Gerald U. Merckel - Delray FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

371 67

Abstract:

A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

US Patent:

55107400, Apr 23, 1996

Filed:

Jul 11, 1994

Appl. No.:

8/272879

Inventors:

Robert Farrell - Hillsborough NJ
Sharad Mehrotra - Tempe AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 513

US Classification:

327142

Abstract:

A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.

US Patent:

43441327, Aug 10, 1982

Filed:

Dec 14, 1979

Appl. No.:

6/103782

Inventors:

Jerry D. Dixon - Boca Raton FL
Robert H. Farrell - Coral Springs FL
Francis R. Koperda - Delray Beach FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300
G06F 506

US Classification:

364200

Abstract:

Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.

US Patent:

55193455, May 21, 1996

Filed:

Jan 26, 1995

Appl. No.:

8/378920

Inventors:

Robert Farrell - Hillsborough NJ
Himanshu Sanghavi - Chandler AZ
Ashish Pandya - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 190175
H03K 1920

US Classification:

327108

Abstract:

Reconfigurable interrupt circuitry may provide differing interrupt output signals to various interrupt receiving devices which are adapted to be driven by interrupt circuits having differing drive characteristics. Control signals representative of the device characteristics of the interrupt receiving device are applied to the reconfigurable interrupt circuitry and output characteristics of the reconfigurable interrupt circuitry are selected according to the control signals. In this manner the reconfigurable interrupt circuitry may by adapted to drive interrupt receiving devices which are compatible with active high interrupt output, active low interrupt output, open drain interrupt output, totem pole interrupt output, tristate interrupt output and non tristate interrupt output. The selected configuration of the reconfigurable interrupt circuitry is determined by writing to registers which may be placed within the memory space of external devices so that the external devices may configure the interrupt according to their own characteristics.

US Patent:

56641532, Sep 2, 1997

Filed:

Aug 30, 1995

Appl. No.:

8/521007

Inventors:

Robert Farrell - Hillsborough NJ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711154

Abstract:

When writing a computer program which accesses a page of memory a programmer may know whether the next memory access is likely to be in the same page of memory. According to a preferred embodiment, program instructions indicate whether the next access is likely to be in the same page of memory. When these instructions are assembled, the assembler puts page control information in an unused high order address bit of the memory access. When the program is executed a memory controller in the system executing the program reads this page control bit and determines whether to close the page after access or leave it open for the next access bit.

US Patent:

59534117, Sep 14, 1999

Filed:

Dec 18, 1996

Appl. No.:

8/767360

Inventors:

Robert L. Farrell - Hillsborough NJ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04M 158

US Classification:

379410

Abstract:

Input/output sample correlation is achieved through the use of first and second correlation tags appended to input and output buffers, respectively. As an output buffer of output samples is prepared, the first correlation tag identifies one of tie output samples in that buffer. As input samples are input and placed into an input buffer, a second correlation tag is appended to the input buffer which identifies the input sample that is input at the time the output sample identified by the first correlation tag is output. Accordingly, a correlation between input and output samples can be used in an echo cancellation operation or the like.

US Patent:

56405430, Jun 17, 1997

Filed:

Apr 1, 1996

Appl. No.:

8/625985

Inventors:

Robert Farrell - Hillsborough NJ
Louis Lippincott - Roebling NJ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1516

US Classification:

395502

Abstract:

Scalable platform architecture includes a high bandwidth bus for transmitting data at high bit rates between various video processing subsystems. A graphics processing subsystem, having graphics memory, is coupled to the high bandwidth bus. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The high bandwidth bus is provided with expansion connectors for detachably coupling to various subsystems. These subsystems may include a video processing subsystem and a video capture system. The high bandwidth bus is also provided with a bus bridge for coupling the high bandwidth bus to a low bandwidth bus or a central processing unit bus.

Address:

1075 Corkwood St, Hollywood, FL 33019

VIN:

3VWRF31Y87M404101

Make:

VOLKSWAGEN

Model:

NEW BEETLE

Year:

2007