Robert Fletcher

US Patent:

44842678, Nov 20, 1984

Filed:

Dec 30, 1981

Appl. No.:

6/335971

Inventors:

Robert P. Fletcher - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516
G06F 900
G06F 1300

US Classification:

364200

Abstract:

The hybrid cache control provides a sharing (SH) flag with each line representation in each private CP cache directory in a multiprocessor (MP) to uniquely indicate for each line in the associated cache whether it is to be handled as a store-in-cache (SIC) line when its SH flag is in non-sharing state, and as a store-through (ST) cache line when its SH flag is in sharing state. At any time the hybrid cache can have some lines operating as ST lines, and other lines as SIC lines. A newly fetched line (resulting from a cache miss) has its SH flag set to non-sharing (SIC) state in its location determined by cache replacement selection circuits, unless the SH flag for the requested line is dynamically set to sharing (ST) state and if a cross-interrogation (XI) hit in another cache is found by cross-interrogation (XI) controls, which XIs all other cache directories in the MP for every store or fetch cache miss and for every store cache hit of a ST line (having SH= 1). A XI hit signals that a conflicting copy of the line has been found in another cache. If the conflicting cache line is changed from its corresponding MS line, the cache line is castout to MS.

US Patent:

44424876, Apr 10, 1984

Filed:

Dec 31, 1981

Appl. No.:

6/336521

Inventors:

Robert P. Fletcher - Poughkeepsie NY
David M. Stein - Pleasantville NY
Irving Wladawsky-Berger - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory levels one and two how a given page of information is to be used. Essentially, pages which can be both written and shared are moved from main memory to the shared level two cache and then to the shared level one cache, with the processors executing from the shared level one cache. All other pages are moved from main memory to the private level two and level one caches of the requesting processor. Thus, a processor executes either from its private or shared level one cache. This allows several processors to share a level three common main memory without encountering cross interrogation overhead.

US Patent:

44451741, Apr 24, 1984

Filed:

Mar 31, 1981

Appl. No.:

6/249526

Inventors:

Robert P. Fletcher - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A control system for interlocking processors in a multiprocessing organization. Each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors. The control system insures that all processors access the most up-to-date copy of memory information with a minimal performance impact. The design allows read only copies of the same shared memory block (line) to exist simultaneously in all private caches. Lines that are both shared and changed are stored in the common shared cache, which each processor can directly fetch from and store into. The shared cache system dynamically detects and moves lines, which are both shared and changed, to the common shared cache and moves lines from the shared cache once sharing has ceased.

US Patent:

44647123, Aug 7, 1984

Filed:

Jul 6, 1981

Appl. No.:

6/280759

Inventors:

Robert P. Fletcher - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1308
G06F 936

US Classification:

364200

Abstract:

The disclosure controls the replacement selection of entries in a second level (L2) cache directory of a storage hierarchy using replaced and hit addresses of a dynamic look-aside translation buffer (DLAT) at the first level (L1) in the hierarchy which receives CPU storage requests along with the CPU cache and its directory. The DLAT entries address page size blocks in main storage (MS). The disclosure provides a replacement (R) flag for each entry in the L2 directory, which represents a page size block in the L2 cache. An R bit is selected and turned on by the address of a DLAT replaced page which is caused by a DLAT miss to indicate its associated page is a candidate for replacement in the L2 cache. However, the page may continue to be accessed in the L2 cache until it is actually replaced. An R bit is selected and turned off by a CPU request address causing a DLAT hit and a L1 cache miss to indicate its associated L2 page is not a candidate for replacement.

US Patent:

44411553, Apr 3, 1984

Filed:

Nov 23, 1981

Appl. No.:

6/324165

Inventors:

Robert P. Fletcher - Poughkeepsie NY
Daniel B. Martin - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

The described embodiment modifies cache addressing in order to decrease the cache miss rate based on a statistical observation that the lowest and highest locations in pages in main storage page frames are usually accessed at a higher frequency than intermediate locations in the pages. Cache class addressing controls are modified to change the distribution of cache contained data more uniformly among the congruence classes in the cache (by comparison with conventional cache class distribution). The cache addressing controls change the congruence class address as a function of the state of a higher-order bit or field in any CPU requested address.

US Patent:

44634200, Jul 31, 1984

Filed:

Feb 23, 1982

Appl. No.:

6/351396

Inventors:

Robert P. Fletcher - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930
G06F 1516
G06F 1300

US Classification:

364200

Abstract:

The disclosure describes a novel cache directory entry replacement method and means for central processors (CPs) in a multiprocessor (MP) based on task identifiers (TIDs) provided in each directory entry to identify the program task which inserted the respective entry. A remote TID register is provided to receive the TID from any remote CP in the MP on each cache miss cross-interrogation hit from any remote CP. Each time a respective CP (i. e. local CP) makes a storage request to its private cache directory, a congruence class in the directory is selected and the TIDs in the selected class are compared to any remote TID in the CP's remote TID register. A TID candidate is any entry in the class which compares equal to the remote TID and is not equal to the current local processor TID. It is identified as a candidate for replacement in the local cache directory on a cache miss. The candidate priorities for replacement in the selected class are: highest priority is any invalid entry, next is any TID candidate, and lowest priority is the conventional LRU candidate.