Robert W Hillman

US Patent:

7415630, Aug 19, 2008

Filed:

Feb 16, 2006

Appl. No.:

11/356945

Inventors:

Robert A. Hillman - San Diego CA, US
Mark Steven Conrad - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 11/00

US Classification:

714 11, 714 12, 714 13

Abstract:

A fault-tolerant computer uses multiple commercial processors operating synchronously, i. e. , in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled.

US Patent:

7437599, Oct 14, 2008

Filed:

Feb 15, 2005

Appl. No.:

11/058136

Inventors:

Robert A. Hillman - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 11/00

US Classification:

714 6

Abstract:

A system and method for effectively implementing an immunity mode in an electronic device includes a processor module for executing processing tasks for the electronic device. The processor module includes processor information, such as processor states and processor data, for executing the processing tasks. The electronic device also includes a protected memory for storing electronic information in an optimally secure manner. An immunity manager may then perform protection procedures to store at least a portion of the vulnerable processor information into the protected memory in response to an immunity mode trigger event such as the processor module entering an idle state.

US Patent:

7467326, Dec 16, 2008

Filed:

Apr 17, 2003

Appl. No.:

10/418713

Inventors:

Robert Allen Hillman - San Diego CA, US
Mark Steven Conrad - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 11/00

US Classification:

714 11, 714 12, 714 13

Abstract:

The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached. The milestone may be a predetermined time interval or any other event that may be defined by a user.

US Patent:

7475326, Jan 6, 2009

Filed:

Jun 4, 2004

Appl. No.:

10/861667

Inventors:

Robert Hillman - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G11C 29/00

US Classification:

714767

Abstract:

A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize oneor more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and/or correction of memory device errors and bit errors in one or more memory devices.

US Patent:

7613948, Nov 3, 2009

Filed:

Feb 19, 2008

Appl. No.:

12/033408

Inventors:

Robert A. Hillman - San Diego CA, US
Mark Steven Conrad - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 11/00

US Classification:

714 11, 714 12, 714 13

Abstract:

A fault-tolerant computer uses multiple commercial processors operating synchronously, i. e. , in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled.

US Patent:

7673186, Mar 2, 2010

Filed:

Jun 7, 2006

Appl. No.:

11/449510

Inventors:

Robert Allen Hillman - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 11/00

US Classification:

714 44, 714 13

Abstract:

Power supply voltage of a PCI or a similar communication bus interface is separated from one or more other power supply voltages on a backplane, on boards insertable into the backplane, and on the bus interface components of the boards. The power supply of the bus interface (VIO) is provided to cold spare boards inserted into the backplane, while the other voltages are not provided to the cold spare boards. Availability of the VIO on the cold spare boards prevents the VIO clamping diodes on the PCI I/O lines from grounding the PCI bus. Cold spare capability is thus provided to systems with PCI and similar communication buses.

US Patent:

7890799, Feb 15, 2011

Filed:

Dec 16, 2008

Appl. No.:

12/336026

Inventors:

Robert A. Hillman - San Diego CA, US
Mark Steven Conrad - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 11/00

US Classification:

714 11, 714 12, 714 13

Abstract:

The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached. The milestone may be a predetermined time interval or any other event that may be defined by a user.

US Patent:

8032889, Oct 4, 2011

Filed:

Apr 5, 2006

Appl. No.:

11/399001

Inventors:

Mark Steven Conrad - San Diego CA, US
Robert A. Hillman - San Diego CA, US

Assignee:

Maxwell Technologies, Inc. - San Diego CA

International Classification:

G06F 9/46
G06F 1/00

US Classification:

718103, 718104, 718107, 713300, 713320, 713323

Abstract:

A method for reducing power consumption and heat generation in a computer system employs a substitute idle task that puts the processor into a dormant mode, e. g. , sleep, nap, or doze mode. The substitute idle task replaces a conventional operating system idle task. The substitute idle task may have a low priority, such as that of the conventional idle task, which it replaces. At each occurrence of a quantum interrupt, a task scheduler schedules applications for execution during the accompanying time slice. After the scheduled applications are done, the substitute idle task is executed. The dormant mode caused by the idle task reduces the system's power consumption. The idle task may also have a high priority and be designed to run for a predetermined percentage of time. Because the processor spends the predetermined percentage of time in the dormant mode, known power consumption reduction may be guaranteed in the system.