Robert D Hopkins

Address:

5320 Live Oak St, Dallas, TX 75206

VIN:

JHLRE38347C005660

Make:

HONDA

Model:

CR-V

Year:

2007

US Patent:

7292050, Nov 6, 2007

Filed:

Aug 23, 2006

Appl. No.:

11/509245

Inventors:

Alex Chow - Palo Alto CA, US
Ronald Ho - Mountain View CA, US
Robert D. Hopkins - Hayward CA, US

Assignee:

Sun Microsystems, Inc - Santa Clara CA

International Classification:

G01R 27/26

US Classification:

324681, 324686, 702179

Abstract:

A method for determining misalignment between two semiconductor dies is described in which signals are transmitted through a first subset of an array of proximity connectors that are proximate to a surface of one of the semiconductor dies and received through a second subset of an array of proximity connectors that are proximate to a surface of the other semiconductor die. A spatial beat frequency is determined from the received signals. This spatial beat frequency corresponds to misalignment-induced aliasing of spatial frequencies associated with the first subset of the array of proximity connectors and the second subset of the array of proximity connectors. The misalignment is then determined using the spatial beat frequency.

US Patent:

D573476, Jul 22, 2008

Filed:

Nov 21, 2007

Appl. No.:

29/297894

Inventors:

Robert L. Hopkins - Dallas TX, US

International Classification:

0901

US Classification:

D 9538, D9537

US Patent:

7425836, Sep 16, 2008

Filed:

Aug 23, 2006

Appl. No.:

11/509246

Inventors:

Alex Chow - East Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Justin M. Schauer - Palo Alto CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 27/26

US Classification:

324681, 324686

Abstract:

In a method for determining capacitance, a first time-varying signal is driven on a first terminal of a first capacitor and a second time-varying signal is driven on a first terminal of a second capacitor, where the first time-varying signal and the second time-varying signal have a pre-determined phase relationship with each other. These signals are received on second terminals of the first capacitor and the second capacitor and demodulated using a periodic signal to produce demodulated signals. This periodic signal has the same fundamental frequency as the first time-varying signal and the second time-varying signal. A DC component in the demodulated signals is then determined by filtering the demodulated signals, and the sign of the DC component is used to determine a relative capacitance of the first capacitor and the second capacitor.

US Patent:

7636361, Dec 22, 2009

Filed:

Sep 27, 2005

Appl. No.:

11/242113

Inventors:

Jo C. Ebergen - San Francisco CA, US
Justin M. Schauer - Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Ivan E. Sutherland - Santa Monica CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

3703954, 370236

Abstract:

One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO. By operating the control paths in parallel in the predetermined sequence, the system does not have to wait a request-acknowledge cycle time between the sender and the receiver before sending consecutive data items through the shared data path, but can instead send multiple data items through the shared data path within a single request-acknowledge cycle time.

US Patent:

7649255, Jan 19, 2010

Filed:

Dec 6, 2006

Appl. No.:

11/635336

Inventors:

Alex Chow - East Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Justin M. Schauer - Palo Alto CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 23/34
H01L 23/48

US Classification:

257723, 257773, 257786, 257777, 257E23144, 438 14, 438381

Abstract:

A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.

US Patent:

7659781, Feb 9, 2010

Filed:

Jun 23, 2008

Appl. No.:

12/143991

Inventors:

Alex Chow - East Palo Alto CA, US
Robert J. Drost - Los Altos CA, US
Robert D. Hopkins - Hayward CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03F 3/16

US Classification:

330277, 330291

Abstract:

An active resistor and its use in a negative feedback amplifier allow wide voltage swings on the input and output signals. One embodiment includes parallel pass-gate MOS transistors of opposite conductivity types connected between the input and output nodes. Bootstrapping transistors are connected between the gates of the pass-gate transistors and respective bias voltages. Coupling capacitors are connected between the gates and the output node. Additional coupling capacitors may be connected between the gates and the input node to make the resistor symmetric. In other embodiments, only one pass-gate transistor is used.

US Patent:

7701254, Apr 20, 2010

Filed:

Mar 13, 2008

Appl. No.:

12/047488

Inventors:

Alex Chow - East Palo Alto CA, US
William Stuart Coates - Los Gatos CA, US
Robert David Hopkins - Hayward CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H03K 19/00

US Classification:

326 93, 326 46

Abstract:

The present disclosure involves reconfigurable circuits that include an asynchronous data path with asynchronous control and at least one logic element coupled with the asynchronous data path that allows the circuit to be configured to more than one logical implementation through data and control token. In one particular example, the asynchronous data path with asynchronous control includes an interconnection of memory elements, such as latches, with each memory element including a corresponding asynchronous control element, such as a GasP element. One or more logical elements are coupled at one or more points of the data path, such coupling may involve feed-back, feed-forward, or combinations of both, and may include external data connections. Through distribution of data items and control tokens to the asynchronous data path with asynchronous control, the fixed logical coupling to the data path may be reconfigured to provide various logical arrangements.

US Patent:

7750709, Jul 6, 2010

Filed:

Jan 5, 2007

Appl. No.:

11/651221

Inventors:

Justin M. Schauer - San Francisco CA, US
Robert D. Hopkins - Hayward CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H03H 11/26

US Classification:

327264, 327261, 327268, 327276, 327277, 327278, 438141, 438142

Abstract:

One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.