Robert A Howell

US Patent:

7514301, Apr 7, 2009

Filed:

Sep 21, 2006

Appl. No.:

11/524246

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H01L 21/00
H01L 21/84

US Classification:

438149

Abstract:

A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.

US Patent:

7601620, Oct 13, 2009

Filed:

Sep 21, 2006

Appl. No.:

11/524244

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

H01L 21/00

US Classification:

438517, 438479, 216 2, 257E2132

Abstract:

Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device layer on top of the buried oxide layer, depositing a tensile stressed layer on the silicon device layer so that stressed layer and silicon device layer form a stressed coiling bi-layer, patterning a coiling arm structure on the stressed coiling bi-layer, depositing a metal encapsulation layer on the stressed coiling bi-layer, and releasing the coiling arm structure so that coiling arm coils to form nanocoil. A system for fabricating nanocoils includes a substrate, a coiling arm structure including, a buried oxide layer deposited on the substrate, a stressed coiling bi-layer attached to the buried oxide layer including a silicon device layer that includes one or more devices defined thereon and a stressed nitride layer that provides a tensile coiling stress, and a metal encapsulation layer that protects stressed nitride layer from hydrofluoric (HF) acid used to release the coiling arm structure from the substrate during the wet etch technique so that coiling arm structure coils into nanocoil when released. Improved nanocoils may be fabricated according to these and other methods and systems.

US Patent:

7710235, May 4, 2010

Filed:

Sep 21, 2006

Appl. No.:

11/524245

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

H01F 21/04
H01F 27/28

US Classification:

336225, 336 65, 336117, 336121, 336122, 385 18, 3592241

Abstract:

Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include inductors or traveling wave tubes fabricated from spiral nanocoils. Such applications includes inductors or traveling wave tubes fabricated from a method for fabricating nanocoils with a desired pitch. Such a method includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.

US Patent:

7795647, Sep 14, 2010

Filed:

Mar 29, 2007

Appl. No.:

11/727955

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US
Harvey C. Nathanson - Pittsburgh PA, US
Francis William Hopwood - Severna Park MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

H01L 29/76

US Classification:

257213, 257401

Abstract:

A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.

US Patent:

20080009687, Jan 10, 2008

Filed:

May 25, 2007

Appl. No.:

11/802806

Inventors:

Joseph Smith - Columbia MD, US
Harvey Nathanson - Pittsburgh PA, US
Robert Howell - Silver Spring MD, US
Christopher Kirby - Gambrills MD, US
Carl Freidhoff - New Freedom PA, US

International Classification:

A61B 5/07

US Classification:

600302000, 600365000, 600398000, 600486000, 600504000, 600549000

Abstract:

A coiled bio-medical device has a base layer coiled to form a plurality of concentric cylinders. The base layer comprises an inner surface. The coiled bio-medical includes a bio-sensor arranged on the inner surface of the base layer. The bio-sensor is adapted to collect bio-medical data from an organism. A transmitter is arranged on the inner surface of the base layer and is adapted to transmit the collected bio-medical data.

US Patent:

20170288045, Oct 5, 2017

Filed:

Jun 15, 2017

Appl. No.:

15/624445

Inventors:

BETTINA A. NECHAY - LAIREI MD, US
SHALINI GUPTA - FALLS CHURCH VA, US
MATTHEW RUSSELL KING - LINTHICUM MD, US
ERIC J. STEWART - SILVER SPRING MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
JUSTIN ANDREW PARKE - ELLICOTT CITY MD, US
HARLAN CARL CRAMER - COLUMBIA MD, US
HOWELL GEORGE HENRY - ELLICOTT CITY MD, US
RONALD G. FREITAG - CATONSVILLE MD, US
KAREN MARIE RENALDO - PASADENA MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 29/778
H01L 29/66
H01L 29/205
H01L 29/15
H01L 29/20

Abstract:

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

US Patent:

20160336425, Nov 17, 2016

Filed:

Jul 28, 2016

Appl. No.:

15/222039

Inventors:

BETTINA A. NECHAY - LAIREI MD, US
SHALINI GUPTA - FALLS CHURCH VA, US
MATTHEW RUSSELL KING - LINTHICUM MD, US
ERIC J. STEWART - SILVER SPRING MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
JUSTIN ANDREW PARKE - ELLICOTT CITY MD, US
HARLAN CARL CRAMER - COLUMBIA MD, US
HOWELL GEORGE HENRY - ELLICOTT CITY MD, US
RONALD G. FREITAG - CATONSVILLE MD, US
KAREN MARIE RENALDO - PASADENA MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 29/66
H01L 29/205
H01L 21/3065
H01L 29/10

Abstract:

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

US Patent:

20160126340, May 5, 2016

Filed:

Nov 5, 2014

Appl. No.:

14/533752

Inventors:

BETTINA A. NECHAY - LAIREI MD, US
SHALINI GUPTA - FALLS CHURCH VA, US
MATTHEW RUSSELL KING - LINTHICUM MD, US
ERIC J. STEWART - SILVER SPRING MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
JUSTIN ANDREW PARKE - ELLICOTT CITY MD, US
HARLAN CARL CRAMER - COLUMBIA MD, US
HOWELL GEORGE HENRY - ELLICOTT CITY MD, US
RONALD G. FREITAG - CATONSVILLE MD, US
KAREN MARIE RENALDO - PASADENA MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 29/778
H01L 29/10
H01L 29/66

Abstract:

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.