Robert Earl Justice

US Patent:

20100262805, Oct 14, 2010

Filed:

Mar 29, 2010

Appl. No.:

12/749065

Inventors:

Robert Sean Justice - Chandler AZ, US
Tyler Nye Boddie - Gilbert AZ, US
Joseph Triece - Phoenix AZ, US

International Classification:

G06F 9/305
G06F 9/22
G06F 13/24
G06F 3/00

US Classification:

712 37, 712223, 710260, 710 51, 712E09023, 712E09018, 712E09004

Abstract:

A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.