Robert T Macomber

US Patent:

6353866, Mar 5, 2002

Filed:

Jan 7, 1998

Appl. No.:

09/003925

Inventors:

David J. Fensore - New Gloucester ME
Kent Bruce Waterson - South Portland ME
Gregory Lewis Dean - Standish ME
Robert Macomber - Portland ME

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710104, 710 8

Abstract:

A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.

US Patent:

6415343, Jul 2, 2002

Filed:

Sep 19, 2001

Appl. No.:

09/955618

Inventors:

David J. Fensore - New Gloucester ME
Kent Bruce Waterson - South Portland ME
Gregory Lewis Dean - Standish ME
Robert Macomber - Portland ME

Assignee:

National Semicondoctor Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710104, 710 9

Abstract:

A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.

US Patent:

7519789, Apr 14, 2009

Filed:

Jan 20, 2005

Appl. No.:

11/039366

Inventors:

Robert L. Macomber - Portland ME, US
David J. Fensore - New Gloucester ME, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1/26
H03K 5/19
G11C 7/00

US Classification:

711167, 327 24, 365221

Abstract:

A method for dynamically selecting a clock edge for recovering read data received from a slave at a master is provided that includes determining whether an internal clock signal is high when a first bit of read data is received at the master. One of a falling edge and a rising edge of the internal clock signal are selected for recovering the read data based on the determination of whether the internal clock signal is high when the first bit of read data is received at the master.

US Patent:

7643593, Jan 5, 2010

Filed:

Oct 14, 2005

Appl. No.:

11/250591

Inventors:

Robert L. Macomber - Portland ME, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H04B 1/16
H04L 7/00

US Classification:

375355, 455255, 455259, 455208

Abstract:

A method for recovering data includes generating a plurality of out-of-phase clock signals. The method also includes generating samples of an incoming data signal, where a plurality of samples are generated using each of the plurality of clock signals. The method further includes selecting one of the plurality of clock signals and providing the samples generated using the selected clock signal. The incoming data signal may be received over a serial interface that includes a clock line for transporting a main clock signal. The out-of-phase clock signals could be approximately 0, 90, 180, and 270 out-of-phase with respect to the main clock signal. The out-of-phase clock signals could be used to clock different registers that sample the incoming data signal. The selected clock signal could be selected by identifying a transition that occurs between samples associated with two of the clock signals and then selecting another of the clock signals.

US Patent:

7877529, Jan 25, 2011

Filed:

Jan 31, 2005

Appl. No.:

11/047311

Inventors:

David J. Fensore - New Gloucester ME, US
Robert L. Macomber - Portland ME, US
James E. Schuessler - Grass Valley CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 5/00
G11B 5/00

US Classification:

710 61, 710 30, 710 71, 714700, 714727, 714731, 711201, 375145, 375149, 370366, 370368

Abstract:

Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in each segment. The synchronization management bits are programmed such that the synchronization management bits contained in first and second adjacent segments of the serial data stream will bear a predetermined relationship to one another. At the receiving end, the synchronization management bits are examined from segment to segment. In this manner, synchronization can be monitored, synchronization loss can be detected, and synchronization recovery can be achieved.

US Patent:

59130717, Jun 15, 1999

Filed:

Jul 26, 1993

Appl. No.:

8/097438

Inventors:

Robert Macomber - Portland ME

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

3958004

Abstract:

A peripheral device and a host device implement a scalar interrupt-acknowledgement system. The peripheral device detects events and increments an unprocessed counter in response to each detected event. The host device processes the events and increments a processed counter in response to each processed event. After a number of events have been processed, the host device transmits the value held by the processed counter to the peripheral device. In response, the peripheral device subtracts the value of the processed counter from the value of the unprocessed counter. The peripheral device asserts an interrupt when events remain to be processed and deasserts the interrupt when all the events have been processed.