Robert P Mcgrath

US Patent:

61693189, Jan 2, 2001

Filed:

Feb 23, 1998

Appl. No.:

9/028072

Inventors:

Robert Daniel McGrath - Andover MA

Assignee:

Polaroid Corporation - Cambridge MA

International Classification:

H01L 2972

US Classification:

257445

Abstract:

An improved pixel design for a CMOS image sensor with a small feature size is described. In conventional image sensors of this type, the quantum efficiency is typically reduced as a result of the decreased thickness of the top n-type layer of the photodiode and the presence of an intervening p-type layer which is higher doped than the substrate. In the pixel design of the invention, the higher doped p-type layer underneath the photodiode is omitted while barrier regions channel the carriers generated by the impinging radiation towards the top n-layer of the photodiode. A high quantum efficiency is thereby attained in spite of a shrinking feature size. The novel pixel design can also incorporate anti-blooming protection.

US Patent:

20210327952, Oct 21, 2021

Filed:

Nov 21, 2018

Appl. No.:

17/273191

Inventors:

- San Jose CA, US
Robert Daniel McGrath - Lexington MA, US

International Classification:

H01L 27/148
H01L 27/146

Abstract:

A system is provided for time delay integration in complementary metal oxide semiconductor imaging sensors, the system comprising: a two dimensional parallel charge transfer structure comprising at least one column of CMOS Image sensor pinned photodiodes; each the diode in the column being connected to the next the diode by a two phase transfer gate, each the transfer gate having a barrier and a well configured such that a flow of charge in the column is unidirectional.

US Patent:

20200161374, May 21, 2020

Filed:

Nov 21, 2018

Appl. No.:

16/198247

Inventors:

- San Jose CA, US
Robert Daniel McGrath - Lexington MA, US

Assignee:

BAE Systems Imaging Solutions Inc. - San Jose CA

International Classification:

H01L 27/30
H01L 27/146

Abstract:

A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.