Robert R Mclaughlin

US Patent:

6982483, Jan 3, 2006

Filed:

May 30, 2003

Appl. No.:

10/448548

Inventors:

Robert J. McLaughlin - Phoenix AZ, US
Alexander J. Elliott - Tempe AZ, US
Mall Mahalingam - Scottsdale AZ, US
Scott D. Marshall - Chandler AZ, US
Pierre-Marie J. Piel - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/34

US Classification:

257728, 257701

Abstract:

The disclosures made herein relate to RF power semiconductor devices. In accordance with one embodiment of the disclosures made herein, a RF power plastic semiconductor device comprises a semiconductor (RF) device, a Low Temperature Co-Fired Ceramic (LTCC) impedance matching structure electrically connected to the RF device and a plastic package body formed over the RF device and the impedance matching structure. The LTCC impedance matching structure comprises a metallized layer overlying a major body portion of the impedance matching structure and comprises a passivation layer on the metallized layer. The passivation layer enhances bond strength of a mold compound of the plastic package body to the metallized layer. Portions of the metallized layer are exposed through the passivation layer for enabling electrical interconnects to be formed between the LTCC impedance matching structure and the RF device. Preferably, RF power plastic packages in accordance with embodiments of the disclosures made herein exhibit terminal impedance of at least about twice that of conventional RF power plastic packages.

US Patent:

59201134, Jul 6, 1999

Filed:

Jul 25, 1997

Appl. No.:

8/900658

Inventors:

Hin Kooi Chee - Seremban NS, MY
Chee Hiong Chew - Seremban NS, MY
Hou Boon Tan - Seremban NS, MY
Robert J. McLaughlin - Phoenix AZ
David M. Culbertson - Tempe AZ
Alex J. Elliott - Tempe AZ
Keng Guan Quah - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 23495

US Classification:

257666

Abstract:

A leadframe (1) includes a main frame having longitudinal outer rails (4) and a number of sub-frame (8) separated from the main frame by a slit (6) extending around at least part of the perimeter of the sub-frame (8). A plurality of flag portions (2), on which a semiconductor die is to be mounted, extend from the mainframe and a plurality of lead portions (12) extend from the sub-frame (8) towards the flag portions (2). The sub-frame (8) is bent twice in a zig-zag fashion so as to be in a plane parallel to that of the main frame so that the corresponding flag and lead portions overlap without affecting the dimensions of the outer edge portion of the main frame.