Robert E Newman

Address:

13058 Lanier Rd, Jacksonville, FL 32226

VIN:

1GNFC16027J153263

Make:

CHEVROLET

Model:

SUBURBAN

Year:

2007

US Patent:

RE37494, Jan 1, 2002

Filed:

Sep 17, 1993

Appl. No.:

08/122934

Inventors:

Antonio Cantoni - North Perth, AU
Robert M. Newman - Santa Clara CA

Assignee:

QPSX Communications Pty. Ltd.

International Classification:

H04J 324

US Classification:

370395, 370471, 370474, 34082504, 34082552

Abstract:

A method and apparatus for transmitting variable length messages on a network in fixed length slots including the provision of a source identifier field in the header of each slot, the source identifier field including a code which is uniquely associated with the message to be transmitted. The fixed length slots are then transmitted on the network and reassembly of the slots by a reassembly machine is controlled in accordance with the identifier codes in the slot.

US Patent:

6426290, Jul 30, 2002

Filed:

Aug 18, 2000

Appl. No.:

09/641351

Inventors:

Valerie Vivares - Palo Alto CA
Robert Newman - Santa Clara CA
Edwin R. Fontecha - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438678, 438108, 438125, 205123, 205125, 205162, 205163, 205164, 205166, 205167

Abstract:

A method of electroplating both sides of a dual-sided circuit board substrate having electrically connected, multi-trace circuit patterns formed on both sides of the substrate, without requiring formation and at least partial removal of electrically conductive tie bars, comprises steps of covering and electrically contacting a first one of the circuit patterns with a first layer of electrically conductive material, applying an electrical potential to the first layer of electrically conductive material to effect electroplating on the second one of the circuit patterns, removing the first layer of electrically conductive material, covering and electrically contacting the second one of the circuit patterns with a second layer of electrically conductive material, applying an electrical potential to the second layer of electrically conductive material to effect electroplating on the first one of the circuit patterns, and removing the second layer of electrically conductive material.

US Patent:

6432291, Aug 13, 2002

Filed:

Aug 18, 2000

Appl. No.:

09/641434

Inventors:

Valerie Vivares - Palo Alto CA
Robert Newman - Santa Clara CA
Edwin R. Fontecha - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

C25D 502

US Classification:

205125, 205163, 205165, 205167

Abstract:

A method of simultaneously electroplating both sides of a dual-sided circuit board substrate having electrically connected, multi-trace circuit patterns formed on both sides of the substrate, without requiring formation and at least partial removal of electrically conductive tie bars and associated extensions, comprises steps of simultaneously electrically contacting each feature of a first one of the circuit patterns with a multi-fingered electrical contactor, and applying an electrical potential to the contactor to effect simultaneous electroplating on the circuit patterns on both sides of the substrate. According to an embodiment of the invention, the multi-fingered contactor comprises an array of electrically conductive wires, rods, or filaments extending from one surface of a metal plate. The invention finds particular utility in the fabrication of ball grid array (BGA) semiconductor device packages.

US Patent:

6661102, Dec 9, 2003

Filed:

Jan 18, 2002

Appl. No.:

10/053994

Inventors:

Robert A. Newman - Santa Clara CA
Jaime D. Weidler - Sunnyvale CA

Assignee:

Advance Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 23495

US Classification:

257787, 257783, 257793, 257674, 257676, 257795, 257790

Abstract:

A semiconductor packaging apparatus for preventing cracking and delamination in a packaged semiconductor chip by controlling the die attach fillet height. Specifically, the present invention controls the die attach material height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself. Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, neither thermal performance nor electrical performance is compromised.

US Patent:

6842662, Jan 11, 2005

Filed:

Apr 4, 2003

Appl. No.:

10/407754

Inventors:

Jaime D. Weidler - Sunnyvale CA, US
Robert A. Newman - Santa Clara CA, US
Jinsu Kwon - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1900
H01L 2166

US Classification:

700121, 438 15

Abstract:

A method and an apparatus for preventing misalignment of semiconductor packaging assembly materials. In particular, a method of fabricating a fully aligned flip-chip assembly having a variable pitch packaging substrate, involves: providing a set of input data; calculating a set of intermediate data using the input data set; calculating a set of final substrate pad coordinates using the intermediate data set, thereby providing a set of output data; providing a packaging substrate having a plurality of substrate pads thereon formed according to the output data set to compensate for any inchoate thermogeometric hysteresis arising from any mismatched coefficients of thermal expansion, and thereby fabricating the flip-chip assembly having a variable pitch packaging substrate, and an assembly thereby fabricated which is more robust to any temperature-induced stress.

US Patent:

6983438, Jan 3, 2006

Filed:

Aug 23, 2000

Appl. No.:

09/643847

Inventors:

Robert Newman - Santa Clara CA, US
Pranabendra Sarma - San Jose CA, US
Valerie Vivares - Palo Alto CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 8

Abstract:

A method and software relating to determining whether a square die fits into a package without generating drawings. Package parameters are defined and used to calculate die characteristics. Calculated die characteristics are compared to defined package parameters and/or to calculated package parameters to make a determination of whether a die with the calculated characteristics fits into a package as defined by its parameters. The method and software allow design of dies to fit packages, the design of packages to fit dies, and simultaneous design of dies and packages that fit one another.

US Patent:

20040046253, Mar 11, 2004

Filed:

Aug 8, 2003

Appl. No.:

10/637419

Inventors:

Robert Newman - Santa Clara CA, US
Jaime Weidler - Sunnyavle CA, US

International Classification:

H01L023/48

US Classification:

257/734000

Abstract:

A method and an apparatus for preventing cracking and delamination in a packaged semiconductor chip by controlling the die attach fillet height. Specifically, the present invention controls the die attach material height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself. Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, neither thermal performance nor electrical performance is compromised.

US Patent:

20100015762, Jan 21, 2010

Filed:

Jul 15, 2008

Appl. No.:

12/173105

Inventors:

Mohammad Khan - Saratoga CA, US
Ranjit Gannamani - San Jose CA, US
Charlie Zhai - San Jose CA, US
Shirsho Sengupta - Santa Clara CA, US
Robert Newman - Santa Clara CA, US

International Classification:

H01L 21/56

US Classification:

438124, 257E21503

Abstract:

Various solder interconnect methods and apparatus are disclosed. In aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a circuit board with plural solder joints whereby an interstitial space is left between the semiconductor chip and the circuit board. The semiconductor chip and the circuit board are heated at a first temperature lower than a melting point of constituents of the plural solder joints to liberate contaminants from the interstitial space. The semiconductor chip and the circuit board are heated again at a second temperature higher than a melting point of at least one the constituents but not all of the constituents of the plural solder joints to shrink grain sizes of the at least one constituent. An underfill is placed in the interstitial space.