Robert L Pitts

US Patent:

6381175, Apr 30, 2002

Filed:

Jan 5, 2001

Appl. No.:

09/755328

Inventors:

Robert L. Pitts - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1604

US Classification:

36518511, 36518533, 711163

Abstract:

A method for validating flash memory includes selecting for execution and executing, from a plurality of setup procedures available for the memory, a memory validation setup procedure setting respective values for a plurality of parameters that are also parameters set by execution of the other of the plurality of setup procedures. The method also includes determining that validation of a particular sector of the flash memory is desired and validating the particular sector of the flash memory, including examining the values of the plurality of parameters.

US Patent:

6449193, Sep 10, 2002

Filed:

Dec 3, 2001

Appl. No.:

09/998727

Inventors:

Andrew Love - Sugarland TX
Robert L. Pitts - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

36518901, 36523001

Abstract:

A more efficient memory access is provided by providing fast access to words on the same physical row (wordline) in memory whether sequential or not, by, after issuance of an address, the detection of whether the current access is on the same physical memory row as the previous access and accordingly allows a different number of wait states, dependent on whether the access is on the same row or not.

US Patent:

6567323, May 20, 2003

Filed:

Feb 15, 2002

Appl. No.:

10/077432

Inventors:

Robert L. Pitts - Dallas TX
Clayton O. Timmons - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365200, 365201, 36518902, 36523002

Abstract:

A memory having flexible column redundancy and flexible row redundancy plural column sticks, each column stick comprising a plurality of data lines. Positioned on either side of the memory are redundant column sticks each comprising a plurality of data lines. A column redundancy control identifies a faulty operating column stick in the memory and generates a column shift control signal to a column shift multiplexer that responds to the column shift control signal to substitute in the memory a redundant column stick for the identified faulty operating column stick. Similar redundant row sticks above and below the normal rows enable a row redundancy controller to signal a row shift multiplexer to replace a faulty operating row stick in the memory.

US Patent:

6608792, Aug 19, 2003

Filed:

Feb 5, 2001

Appl. No.:

09/777180

Inventors:

Robert L. Pitts - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

3652257, 36518504

Abstract:

A circuit ( ) for protecting sensitive data stored in a storage area ( ) includes a one time programmable device such as a fuse element ( ) coupled to the input data path ( ), and a one time programmable device such as fuse element ( ) coupled to the output data path ( ). Once sensitive data is loaded into the storage area ( ), either one of, or both of the fuses ( ) can be activated (blown) in order to prevent access to the data stored in storage area ( ). Optionally, a fuse element ( ) can also be added to the internal circuit data line ( ) that would prevent both internal and external access to the stored data.

US Patent:

6614703, Sep 2, 2003

Filed:

Jan 12, 2001

Appl. No.:

09/760287

Inventors:

Robert L. Pitts - Dallas TX
Baher Haroun - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365221, 36523003, 36518508, 36518511, 36518912

Abstract:

A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method comprising: storing a plurality of configuration data in the non-volatile memory and, providing power to the volatile memory. After providing power to the volatile memory, serially loading the configuration data into the registers of the volatile memory to configure the semiconductor device.

US Patent:

6735146, May 11, 2004

Filed:

Sep 10, 2002

Appl. No.:

10/241072

Inventors:

Robert L. Pitts - Dallas TX
David Toops - Terrell TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

36523006, 36523003, 36523008, 36518909, 365206, 365214

Abstract:

In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.

US Patent:

6747481, Jun 8, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/301986

Inventors:

Robert L. Pitts - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 327525

Abstract:

This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become measurably lower resistance.

US Patent:

6876594, Apr 5, 2005

Filed:

Dec 19, 2003

Appl. No.:

10/739520

Inventors:

Roger C. Griesmer - Murphy TX, US
Robert L. Pitts - Dallas TX, US
Bryan D. Sheffield - Rowlett TX, US
Mark J. Jensen - Allen TX, US
Vinod J. Menezes - Bangalore, IN

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C007/00

US Classification:

3652257, 365200, 365 96

Abstract:

An integrated circuit (IC). The integrated circuit comprises an array () of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry () for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry () for reading selected ones of the data cells in a read mode.