Robert E Pryor

US Patent:

6489211, Dec 3, 2002

Filed:

Mar 1, 2000

Appl. No.:

09/516349

Inventors:

Raymond J. Balda - Tempe AZ
Robert A. Pryor - Mesa AZ
James D. Paulsen - Tempe AZ
Robert J. Johnsen - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 218238

US Classification:

438322, 438325, 438327

Abstract:

A method of manufacturing a semiconductor component includes providing a composite substrate ( ) with a dielectric portion and a semiconductor portion and growing an epitaxial layer ( ) over the composite substrate. The epitaxial layer has a polycrystalline portion ( ) over the dielectric portion of the composite substrate and also has a monocrystalline portion ( ) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.

US Patent:

6900105, May 31, 2005

Filed:

Aug 2, 2002

Appl. No.:

10/211842

Inventors:

Raymond J. Balda - Tempe AZ, US
Robert A. Pryor - Mesa AZ, US
Joseph L. Petrucci, Jr. - Dresden, DE
Robert J. Johnsen - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/331

US Classification:

438361, 438353, 438357, 438359, 438360, 438369

Abstract:

In a semiconductor manufacturing method, an emitter region () and a base enhancement region () are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device () is formed on a silicon substrate layer () with an epitaxial layer (). Trenches () are cut into the epitaxial layer () and filled with oxide () to provide reduced junction capacitance and reduced base resistance. The emitter region () and the base enhancement region () are simultaneously formed through an anneal process.

US Patent:

7047309, May 16, 2006

Filed:

Jan 8, 2002

Appl. No.:

10/043053

Inventors:

Gerald Walter Baumann - Surprise AZ, US
Robert Franklin Pryor - Lynn Haven FL, US
Marc Steinbrecher - Boulder CO, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709232, 709231, 709233, 37039541, 37911407, 725 96

Abstract:

Available bandwidth utilization during transfer of large files over a TCP/IP network is improved by load balancing data streams and dynamically controlling the number of data streams utilized. A determination is made of the optimum number of data streams for a particular data file transfer in the early stage of transmission. An initial number of data streams, which is one unless otherwise specified or determined, is used to transmit one or more file segments, each on a different data stream, immediately followed by a second initial number of data streams, which is at least two greater than the initial number of data streams, is used to transmit another portion of the large data file. During each transmission, individual and aggregate transmission bandwidths are determined. Responsive to a determination that the latest aggregate transmission bandwidth is significantly different from the previous aggregate transmission bandwidth, the number of data streams is modified.

US Patent:

7368668, May 6, 2008

Filed:

Feb 3, 2006

Appl. No.:

11/347461

Inventors:

Xiaowei Ren - Phoenix AZ, US
Robert A. Pryor - Mesa AZ, US
Daniel J. Lamey - Phoenix AZ, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

H05K 9/00

US Classification:

174382, 174377, 257659

Abstract:

A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.

US Patent:

7525152, Apr 28, 2009

Filed:

Feb 23, 2007

Appl. No.:

11/678330

Inventors:

Christopher P. Dragon - Tempe AZ, US
Wayne R. Burger - Phoenix AZ, US
Robert A. Pryor - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/76

US Classification:

257341, 257401, 257E2912

Abstract:

An RF power transistor with a metal design () comprises a drain pad () and a plurality of metal drain fingers () extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (-----), each section of metal including of one or more branch (-------) of metal having a metal width maintained within a bamboo regime.

US Patent:

20080150022, Jun 26, 2008

Filed:

Dec 20, 2007

Appl. No.:

11/961426

Inventors:

Robert A. Pryor - Mesa AZ, US
Gabriele F. Formicone - Chandler AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 21/336
H01L 29/78

US Classification:

257341, 438286, 257E29256, 257E21417

Abstract:

A power transistor comprises a number of groups of gate fingers of various widths and can include uniform or non-uniform pitch. The widths may include any number of different widths. In one embodiment, there are included three widths W, W, and W, in which W>W>W. The groups of gate fingers are arranged from greater width to lesser width disposed from a periphery to a center of the device. In addition, the gate fingers are configured to have one of a centered justification, a gate pad side justification, and a drain pad side justification, along a dimension of the power transistor layout. In another embodiment, the groups of gate fingers having widths W, W, and Ware configured symmetrically about a center line of the device. The variable gate finger widths provide a level of greater power density at the outside of the die in relation to a power density at the center of the die. Asymmetrical arrangements of gate finger widths are also contemplated.

US Patent:

20120037969, Feb 16, 2012

Filed:

Aug 12, 2010

Appl. No.:

12/855479

Inventors:

Paul W. Sanders - Scottsdale AZ, US
Wayne R. Burger - Phoenix AZ, US
Thuy B. Dao - Austin TX, US
Joel E. Keys - Austin TX, US
Michael F. Petras - Phoenix AZ, US
Robert A. Pryor - Mesa AZ, US
Xiaowei Ren - Phoenix AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 27/06
H01L 21/82

US Classification:

257296, 257531, 438393, 257E27016, 257E21602

Abstract:

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates () and lower resistance inductors (′) for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--″) overlying the substrate (). The active transistor(s) (′) are formed in the substrate () proximate the front face (). Planar capacitors (′) are also formed over the front face () of the substrate (). Various terminals (------′, etc.) of the transistor(s) (′), capacitor(s) (′) and inductor(s) (′) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (′) and heavy current carrying conductors (-′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

US Patent:

41314883, Dec 26, 1978

Filed:

Apr 25, 1977

Appl. No.:

5/792438

Inventors:

Israel A. Lesk - Scottsdale AZ
Robert A. Pryor - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21263
H01L 3104

US Classification:

148 15

Abstract:

This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers. The device is designed to permit solder contacts to be made to the P and N regions thereof without possibility of shorting to semiconductor regions of opposite type conductivity.