Robert L Reese

Address:

5207 Walsh St, Saint Louis, MO 63109

VIN:

KNAFE221195662132

Make:

KIA

Model:

SPECTRA

Year:

2009

US Patent:

6735543, May 11, 2004

Filed:

Nov 29, 2001

Appl. No.:

09/996839

Inventors:

Steven Michael Douskey - Rochester MN
Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex Junction VT
Curtis Walter Preuss - Rochester MN
Robert James Reese - Austin TX
Paul William Rudrud - Rochester MN
James Donald Ryan - Rochester MN
Robert Russell Williams - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1900

US Classification:

702120, 702123, 702126, 702185, 326 30, 326 31, 326 86, 714715, 714724, 714728, 324601, 324712, 324 7655, 324 7682, 716 1, 716 4

Abstract:

An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

US Patent:

6762626, Jul 13, 2004

Filed:

Apr 24, 2003

Appl. No.:

10/422686

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex Junction VT
Kevin Charles Gower - LaGrangeville NY
Gary Alan Peterson - Rochester MN
Robert James Reese - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03D 900

US Classification:

327 2, 327 3

Abstract:

A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (âguardbandsâ). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

US Patent:

7012956, Mar 14, 2006

Filed:

Feb 11, 2005

Appl. No.:

11/055835

Inventors:

Peter M. Thomsen - Austin TX, US
Robert J. Reese - Austin TX, US
Hector Saenz - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 17/00

US Classification:

375224, 375354

Abstract:

Delay circuits have programmable delay elements to delay data signals so a clock samples the data signals in the middle of the eye window pattern. The clock is frequency divided by two, generating a divided clock coupled to a clock delay circuit and a data delay circuit generating a toggle clock and a delayed toggle clock that are sampled with the clock signal. A state machine varies the number N of delay elements selected in the data delay circuit until successive samples of the toggle clock and the delay toggle clock have opposite logic stages. The resulting number N is the number of delay elements required to generate a delay equal to one period of the clock. The delay of each delay element is adjusted using adjustment control signals until an N is generated that is within a predetermined range. The adjustment control signals are distributed to the data delay circuits.

US Patent:

7080288, Jul 18, 2006

Filed:

Apr 28, 2003

Appl. No.:

10/425423

Inventors:

Frank David Ferraiolo - Essex Junction VT, US
Michael Stephen Floyd - Austin TX, US
Robert James Reese - Austin TX, US
Kevin Franklin Reick - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/22

US Classification:

714 43, 714 56, 714700

Abstract:

A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

US Patent:

7129859, Oct 31, 2006

Filed:

Jul 22, 2004

Appl. No.:

10/896504

Inventors:

Daniel M. Dreps - Georgetown TX, US
Robert J. Reese - Austin TX, US
Hector Saenz - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 7/00

US Classification:

341 50, 380 46

Abstract:

Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

US Patent:

7230449, Jun 12, 2007

Filed:

Feb 11, 2005

Appl. No.:

11/055805

Inventors:

Daniel M. Dreps - Georgetown TX, US
Frank D. Ferraiolo - New Windsor NY, US
Robert J. Reese - Austin TX, US
Glen A. Wiedemeier - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16
H04B 3/00
H04L 25/00

US Classification:

326 30, 326 86, 326 29, 375257

Abstract:

Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.

US Patent:

7246332, Jul 17, 2007

Filed:

Feb 8, 2005

Appl. No.:

11/053078

Inventors:

Joseph David Mendenhall - Cary NC, US
John Christopher Morris - Durham NC, US
Robert James Reese - Austin TX, US
Chad Everett Winemiller - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 703 13

Abstract:

Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.

US Patent:

7412618, Aug 12, 2008

Filed:

Feb 11, 2005

Appl. No.:

11/055817

Inventors:

Frank D. Ferraiolo - New Windsor NY, US
Robert J. Reese - Austin TX, US
Michael B. Spear - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04

US Classification:

713600, 713401, 375372

Abstract:

An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.