Robert M Reese

US Patent:

7012956, Mar 14, 2006

Filed:

Feb 11, 2005

Appl. No.:

11/055835

Inventors:

Peter M. Thomsen - Austin TX, US
Robert J. Reese - Austin TX, US
Hector Saenz - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 17/00

US Classification:

375224, 375354

Abstract:

Delay circuits have programmable delay elements to delay data signals so a clock samples the data signals in the middle of the eye window pattern. The clock is frequency divided by two, generating a divided clock coupled to a clock delay circuit and a data delay circuit generating a toggle clock and a delayed toggle clock that are sampled with the clock signal. A state machine varies the number N of delay elements selected in the data delay circuit until successive samples of the toggle clock and the delay toggle clock have opposite logic stages. The resulting number N is the number of delay elements required to generate a delay equal to one period of the clock. The delay of each delay element is adjusted using adjustment control signals until an N is generated that is within a predetermined range. The adjustment control signals are distributed to the data delay circuits.

US Patent:

7887207, Feb 15, 2011

Filed:

Mar 15, 2006

Appl. No.:

11/886033

Inventors:

Riad Saraiji - Falls Church VA, US
Mark A. Daniels - Manlius NY, US
Robert J. Reese - Spartanburg SC, US
Stephen Kenney - North Syracuse NY, US
Thomas E. Drago - Liverpool NY, US

Assignee:

Carrier Corporation - Farmington CT

International Classification:

F21S 2/00

US Classification:

362 92, 362 94, 362133

Abstract:

The display space of a multiple door display merchandiser is illuminated by one or more vertically extending lamps () disposed intermediate the vertical sides of an access opening to the display space. A multiple door assembly () covers the access opening. To enhance the illumination of the display space, a pair of vertically extending side reflectors () are provided, one extending along one side of the access opening and the other extending along the other side of the access opening. An additional reflector may be mounted to an interior facing surface of the door along an upper front region of the door and/or a lower front region.

US Patent:

20090276559, Nov 5, 2009

Filed:

May 2, 2008

Appl. No.:

12/114533

Inventors:

Robert J. Reese - Austin TX, US
Michael B. Spear - Round Rock TX, US
Peter M. Thomsen - Hutto TX, US
Michael R. Trombley - Cary NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/06

US Classification:

711 5, 711E12081

Abstract:

In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

US Patent:

57403996, Apr 14, 1998

Filed:

Aug 23, 1995

Appl. No.:

8/518348

Inventors:

Michael John Mayfield - Austin TX
Trinh Huy Nguyen - Pflugerville TX
Robert James Reese - Austin TX
Michael Thomas Vaden - Austin TX

Assignee:

International Business Machines Corporation

International Classification:

G06F 1208

US Classification:

395464

Abstract:

Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.

US Patent:

56110588, Mar 11, 1997

Filed:

Mar 20, 1996

Appl. No.:

8/619100

Inventors:

Charles R. Moore - Austin TX
John S. Muhich - Austin TX
Robert J. Reese - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314
G06F 1318
G06F 1338

US Classification:

395309

Abstract:

A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic between the first and second buses. Using the logic, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.

US Patent:

62437763, Jun 5, 2001

Filed:

Jul 13, 1998

Appl. No.:

9/114116

Inventors:

George McNeil Lattimore - Austin TX
Robert James Reese - Austin TX
Gus Wai-Yan Yeung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710104

Abstract:

A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i. e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.

US Patent:

61784931, Jan 23, 2001

Filed:

Feb 19, 1998

Appl. No.:

9/026088

Inventors:

Peter Steven Lenk - Austin TX
Michael J. Mayfield - Austin TX
Robert James Reese - Austin TX
Michael Thomas Vaden - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1500

US Classification:

712 28

Abstract:

In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

US Patent:

57581193, May 26, 1998

Filed:

Aug 23, 1995

Appl. No.:

8/518347

Inventors:

Michael John Mayfield - Austin TX
Trinh Huy Nguyen - Pflugerville TX
Robert James Reese - Austin TX
Michael Thomas Vaden - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1208

US Classification:

395449

Abstract:

Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches. A directory field entry provides an indication of whether or not a particular cache line in the L1 cache is also included in the L2 cache.