Robert Andrew Riddle

US Patent:

56530196, Aug 5, 1997

Filed:

Aug 31, 1995

Appl. No.:

8/522471

Inventors:

Anthony F. Bernhardt - Berkeley CA
Robert J. Contolini - Livermore CA
Vincent Malba - Livermore CA
Robert A. Riddle - Tracy CA

Assignee:

Regents of the University of California - Oakland CA

International Classification:

H05K 334

US Classification:

29840

Abstract:

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.