Robert J Robertson

US Patent:

6338874, Jan 15, 2002

Filed:

Dec 14, 1995

Appl. No.:

08/572385

Inventors:

Kam S. Law - Union City CA
Robert Robertson - Palo Alto CA
Pamela Lou - San Francisco CA
Marc Michael Kollrack - Alameda CA
Angela Lee - Sunnyvale CA
Dan Maydan - Los Altos Hills CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1600

US Classification:

42725518, 42725519, 42725527, 42725537, 427255394

Abstract:

Multilayer deposition of thin films onto glass substrates to form thin film transistors can be carried out in the same chamber under similar reaction conditions at high deposition rates. We have found that sequential thin layers of silicon nitride and amorphous silicon can be deposited in the same chamber by chemical vapor deposition using pressure of at least 0. 5 Torr and substrate temperatures of about 250-370Â C. Subsequently deposited different thin films can also be deposited in separate chemical vapor deposition chambers which are part of a single multichamber vacuum system.

US Patent:

6444277, Sep 3, 2002

Filed:

Sep 9, 1994

Appl. No.:

08/303566

Inventors:

Kam S. Law - Union City CA
Robert Robertson - Palo Alto CA
Pamela Lou - San Francisco CA
Marc Michael Kollrack - Alameda CA
Angela Lee - Sunnyvale CA
Dan Maydan - Los Altos Hills CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B05D 306

US Classification:

427574, 427535, 42725518, 42725528, 4272557, 427573

Abstract:

Amorphous silicon thin films can be deposited onto large area glass substrates at high deposition rates by chemical vapor deposition using pressure of at least 0. 8 Torr and temperatures of about 270-350Â C. and fairly high gas flow rates of silane in a hydrogen carrier gas. The spacing between the inlet gas manifold and the substrate in the CVD chamber is maintained so as to maximize the deposition rate. Improved transistor characteristics are observed when the substrate is either exposed to a hydrogen plasma for a few seconds prior to high rate deposition of the amorphous silicon, or when a first layer of amorphous silicon is deposited using a slow deposition rate process prior to deposition of the high deposition rate amorphous silicon.

US Patent:

6610374, Aug 26, 2003

Filed:

Sep 10, 2001

Appl. No.:

09/954797

Inventors:

Takako Takehara - Hayward CA
Regina Qiu - Cupertino CA
Yvonne LeGrice - Mountain View CA
William Reid Harshbarger - San Jose CA
Robert McCormick Robertson - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B05D 306

US Classification:

427554, 427109, 427167, 42725518, 427314, 427379, 4273762

Abstract:

A thin film layer can be formed on a glass substrate by preheating the substrate, depositing an amorphous silicon precursor layer on the substrate at a first temperature, and annealing the substrate in a thermal processing chamber at a second temperature sufficiently higher than the first temperature to substantially reduce the hydrogen concentration in the precursor layer. The preheating and annealing steps can occur in the same thermal processing chamber. Then the precursor layer is converted to a polycrystaline silicon layer by laser annealing.

US Patent:

58611975, Jan 19, 1999

Filed:

Oct 23, 1996

Appl. No.:

8/740012

Inventors:

Kam Law - Union City CA
Robert Robertson - Palo Alto CA
Guofu Jeff Feng - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B05D 306
C23C 1640

US Classification:

427579

Abstract:

A plasma enhanced chemical vapor deposition process for depositing conformal silicon oxide thin films useful to make thin film transistors which have stable electrical properties and low charge centers onto a substrate comprising flowing a precursor gas mixture of silane and nitrous oxide, the latter at a high rate, at a pressure of at least about 0. 8 torr and a temperature of from about 250. degree. to 350. degree. C. The effective volume of the reaction region between the gas manifold inlet and the substrate during processing is kept small.

US Patent:

62942190, Sep 25, 2001

Filed:

Mar 3, 1998

Appl. No.:

9/033868

Inventors:

Takako Takehara - Hayward CA
Regina Qiu - Cupertino CA
Yvonne LeGrice - Mountain View CA
William Reid Harshbarger - San Jose CA
Robert McCormick Robertson - Santa Clara CA

Assignee:

Applied Komatsu Technology, Inc. - Tokyo

International Classification:

B05D 302
C23C 1410
C23C 1624

US Classification:

427314

Abstract:

A thin film layer can be formed on a glass substrate by preheating the substrate, depositing an amorphous silicon precursor layer on the substrate at a first temperature, and annealing the substrate in a thermal processing chamber at a second temperature sufficiently higher than the first temperature to substantially reduce the hydrogen concentration in the precursor layer. The preheating and annealing steps can occur in the same thermal processing chamber. Then the precursor layer is converted to a polycrystaline silicon layer by laser annealing.

US Patent:

54417686, Aug 15, 1995

Filed:

Feb 8, 1994

Appl. No.:

8/193310

Inventors:

Kam S. Law - Union City CA
Robert Robertson - Palo Alto CA
Michael Kollrack - Alameda CA
Angela T. Lee - Sunnyvale CA
Takako Takehara - Hayward CA
Guofu J. Feng - San Jose CA
Dan Maydan - Los Altos Hills CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1622

US Classification:

4272557

Abstract:

An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN. sub. x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon.

US Patent:

53805666, Jan 10, 1995

Filed:

Jun 21, 1993

Appl. No.:

8/080018

Inventors:

Robert Robertson - Palo Alto CA
Marc M. Kollrack - Alameda CA
Angela T. Lee - Sunnyvale CA
Kam Law - Union City CA
Dan Maydan - Los Altos Hills CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B05D 306

US Classification:

427534

Abstract:

A method of limiting sticking of a body (substrate) to a susceptor after the body has been coated with a layer in a deposition chamber by plasma chemical vapor deposition includes subjecting the coated body to a plasma of an inactive gas, e. g. , hydrogen, nitrogen, argon or ammonia, which does not adversely affect the coating and does not add additional layers to the body. After the coated body is subjected to the plasma of the inactive gas, the body is separated from the susceptor.

US Patent:

55892337, Dec 31, 1996

Filed:

Jun 6, 1995

Appl. No.:

8/466915

Inventors:

Kam Law - Union City CA
Robert Robertson - Palo Alto CA
Guofu J. Feng - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1600
B05D 306

US Classification:

427579

Abstract:

A method of depositing layers of intrinsic amorphous silicon and doped amorphous silicon sequentially on a substrate in the same CVD chamber without incurring a dopant contamination problem. The method can be carried out by first depositing an additional layer of a dielectric insulating material prior to the deposition process of the intrinsic amorphous silicon layer. The additional layer of insulating material deposited on the substrate should have a thickness such that residual insulating material coated on the chamber walls is sufficient to cover the residual dopants on the chamber walls left by the deposition process of the previous substrate. This provides a clean environment for the next deposition process of an intrinsic amorphous silicon layer on a substrate in the same CVD chamber.